SBVS257 March   2025 TPS7A56

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Charge Pump Enable and BIAS Rail
      6. 6.3.6 Power-Good Pin (PG Pin)
      7. 6.3.7 Active Discharge
      8. 6.3.8 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
      4. 6.4.4 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Undervoltage Lockout (UVLO) Operation
        1. 7.1.2.1 IN Pin UVLO
        2. 7.1.2.2 BIAS UVLO
        3. 7.1.2.3 Typical UVLO Operation
        4. 7.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 7.1.3  Dropout Voltage (VDO)
      4. 7.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 7.1.5  Recommended Capacitor Types
      6. 7.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 7.1.7  Optimizing Noise and PSRR
      8. 7.1.8  Adjustable Operation
      9. 7.1.9  Load Transient Response
      10. 7.1.10 Charge Pump Operation
      11. 7.1.11 Sequencing
      12. 7.1.12 Power-Good Functionality
      13. 7.1.13 Paralleling for Higher Output Current and Lower Noise
      14. 7.1.14 Power Dissipation (PD)
      15. 7.1.15 Estimating Junction Temperature
      16. 7.1.16 TPS7A57EVM-056 Thermal Analysis
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

6.1 Overview

The TPS7A56 is a low-noise (2.45μVRMS over 10Hz to 100kHz bandwidth), ultra-high PSRR (> 36dB to 1MHz), high-accuracy (1%), ultra-low-dropout (LDO) linear voltage regulator. This device has an input range of 0.7V to 6.0V and an output voltage range from 0.5V to 5.0V. This device uses innovative circuitry to achieve wide bandwidth and high loop gain, resulting in ultra-high PSRR even with very low operational headroom. This headroom is calculable as [VOpHr = (VIN – VOUT)]. At a high level, the device has two main primary features and a few secondary features. The primary features are the current reference and the unity-gain LDO buffer. The secondary features are the adjustable soft-start inrush control, precision enable, charge pump enable, and PG pin.

The current reference is controlled by the REF pin. This pin sets the output voltage with a single resistor.

The NR/SS pin sets the start-up time and filters the noise generated by the reference and external set resistor.

The unity-gain LDO buffer controls the output voltage. The low noise does not increase with output voltage and provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.

Use the low-noise current reference, 50μA typical, in conjunction with an external resistor (RREF) to set the output voltage. This process allows the output voltage range to be set from 0.5V to 5.0V. To achieve low noise and allow for a soft-start inrush, place an external capacitor, CNR/SS (typically 4.7μF), on the NR/SS pin. When start-up is completed and the switch between REF and NR/SS is closed, the CNR/SS capacitor is in parallel with the RREF resistor. This resistor attenuates the band-gap noise and sets the output voltage. This unity-gain LDO provides ultra-high PSRR over a wide frequency range without compromising load and line transients.

The EN pin sets the precision enable feature; a resistor divider on this pin selects the optimal input voltage at which the device starts. There are three independent undervoltage lockout (UVLO) voltages in this device. These voltages are the internal fixed UVLO thresholds for the IN and BIAS rails, and the externally adjustable UVLO threshold using the EN pin.

The CP_EN pin enables or disables the internal charge pump. The TPS7A56 does not allow operation below 1.1V without a BIAS rail. If the charge pump is disabled, a minimum operating headroom between OUT and BIAS is required.

This regulator offers current limit, thermal protection, and is fully specified from –40°C to +125°C. This device is offered in a 16-pin WQFN, 3mm × 3mm thermally efficient package.