SBVS257 March   2025 TPS7A56

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Charge Pump Enable and BIAS Rail
      6. 6.3.6 Power-Good Pin (PG Pin)
      7. 6.3.7 Active Discharge
      8. 6.3.8 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
      4. 6.4.4 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Undervoltage Lockout (UVLO) Operation
        1. 7.1.2.1 IN Pin UVLO
        2. 7.1.2.2 BIAS UVLO
        3. 7.1.2.3 Typical UVLO Operation
        4. 7.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 7.1.3  Dropout Voltage (VDO)
      4. 7.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 7.1.5  Recommended Capacitor Types
      6. 7.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 7.1.7  Optimizing Noise and PSRR
      8. 7.1.8  Adjustable Operation
      9. 7.1.9  Load Transient Response
      10. 7.1.10 Charge Pump Operation
      11. 7.1.11 Sequencing
      12. 7.1.12 Power-Good Functionality
      13. 7.1.13 Paralleling for Higher Output Current and Lower Noise
      14. 7.1.14 Power Dissipation (PD)
      15. 7.1.15 Estimating Junction Temperature
      16. 7.1.16 TPS7A57EVM-056 Thermal Analysis
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

7.1.13 Paralleling for Higher Output Current and Lower Noise

Achieving higher output current and lower noise is achievable by paralleling two or more LDOs. Carefully plan out implementation to optimize performance and minimize output current imbalance.

Because the TPS7A56 output voltage is set by a resistor driven by a current source, adjust the REF resistor and capacitor. The following equations calculate the resistor and capacitor settings.

Equation 6. RREF = VOUT_TARGET / (n × IREF)
Equation 7. CNR/SS_parallel = n × CNR/SS_single

where:

  • n is the number of LDOs in parallel
  • IREF is the REF current as provided in the Electrical Characteristics table
  • CNR/SS_single is the NR/SS capacitor for a single LDO; make sure each LDO has a separate CNR/SS capacitor

The LDO functions as a buffer when connecting the IN pins together. Thus, the current imbalance is only affected by the error offset voltage of the error amplifier. As such, express the current imbalance as:

Equation 8. εI = VOS × 2 × RBALLAST / (RBALLAST2 – ΔRBALLAST2)

where:

  • εI is the current imbalance
  • VOS is the LDO error offset voltage
  • RBALLAST is the ballast resistor
  • ΔRBALLAST is the deviation of the ballast resistor value from the nominal value

Figure 7-10 shows a diagram of multiple devices in parallel.

TPS7A56 Paralleling Multiple TPS7A56 Devices Figure 7-10 Paralleling Multiple TPS7A56 Devices

Using the configuration described, the LDO output noise is reduced by:

Equation 9. eO_parallel = (1 / √n) × eO_single

where:

  • n is the numbers of LDOs in parallel
  • eO_single is the output noise density from a single LDO
  • eO_parallel is the output noise density for the resulting parallel LDO

In Figure 7-10, the noise is reduced by 1/√2.

For more information in paralleling LDOs see: