SCPS299B May   2025  – July 2026 TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8124 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.9 Feature Register Mapping

The TXE8124-Q1 device registers are implemented as a register bank, where the actual register address for a port is formed by concatenating the feature address, 0 and the port number as shown in Figure 7-5. This allows the customer software to configure or read a specific feature for all ports more effectively with a burst transfer.

Table 7-2 lists the registers as per the feature address and support for multi-port.

Table 7-2 TXE8124-Q1 Feature Map
FEATURE ADDRESS REGISTER NAME MULTI PORT ACCESS
B20 B19 B18 B17 B16
0 0 0 0 0 Scratch Register No RW
0 0 0 0 1 Device_ID No R
0 0 0 1 0 Input Port Register Yes R
0 0 0 1 1 Output Port Register Yes RW
0 0 1 0 0 Direction Configuration Register Yes RW
0 0 1 0 1 Polarity Inversion Register Yes RW
0 0 1 1 0 Push Pull / Open Drain Selection Register Yes RW
0 1 0 0 0 Pull Up or Pull Down Enable Register Yes RW
0 1 0 0 1 Pull Up or Pull Down Selection Register Yes RW
0 1 0 1 0 Bus Holder Register Yes RW
0 1 0 1 1 Smart Interrupt Register No RW
0 1 1 0 0 Interrupt Mask Register Yes RW
0 1 1 0 1 Input Glitch Filter Enable Register No RW
0 1 1 1 0 Interrupt Flag Status Register No R
0 1 1 1 1 Interrupt Port Status Register No R
1 0 0 1 0 Fail-safe Enable Register 1 No RW
1 0 0 1 1 Fail-safe Enable Register 2 Yes RW
1 0 1 0 0 Fail-safe Direction Configuration Register 1 Yes RW
1 0 1 0 1 Fail-safe Direction Configuration Register 2 Yes RW
1 0 1 1 0 Fail-safe Output Register 1 Yes RW
1 0 1 1 1 Fail-safe Output Register 2 Yes RW
1 1 0 0 0 Fail-safe Redundancy Check Register No RW
1 1 0 0 1 Fault Status Register No R
1 1 0 1 0 Software Reset Register No WO