SCPS299B May   2025  – July 2026 TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8124 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 SPI Bus Timing Requirements

over operating free-air temperature range and SDO CLOAD = 100pF (unless otherwise noted) (see (Figure 6-3))
MIN MAX UNIT
SPI Bus - 10MHz
fSCLK SPI clock frequency; 3.3V < VCC < 5.5V 10 MHz
tCSS CS to SCLK Rise Setup Time 50 ns
tCSH SCLK Fall to CS De-asserted Hold Time 50 ns
tCSD CS Disable Time 50 ns
tDS SDI to SCLK Setup Time 10 ns
tDH SDI to SCLK Hold Time 10 ns
tLOW SCLK Low Time 45 ns
tHIGH SCLK High Time 45 ns
tV (SDO) SDO Valid Time 27 ns
tDIS (SDO) SDO Disable Time 50 ns
SPI Bus - 5MHz
fSCLK SPI clock frequency; 1.65V < VCC <  5.5V 5 MHz
tCSS CS to SCLK Rise Setup Time 50 ns
tCSH SCLK Fall to CS De-asserted Hold Time 100 ns
tCSD CS Disable Time 100 ns
tDS SDI to SCLK Setup Time 10 ns
tDH SDI to SCLK Hold Time 10 ns
tLOW SCLK Low Time 90 ns
tHIGH SCLK High Time 90 ns
tV (SDO) SDO Valid Time 54 ns
tDIS (SDO) SDO Disable Time 100 ns