SCPS299B May   2025  – July 2026 TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8124 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.4 Bus Hold

TXE8124-Q1 supports bus hold (bus-keeper) function on all input I/Os which is very useful when the system has to go into low-power or standby state as external pullup or pulldown corresponding to the low-power state are no longer required. By default the feature is disabled and must be enabled through software programming.

On enabling the bus hold feature, the I/O holds the last known active level on the I/O. If the external device drives a logic 1, TXE8124-Q1 activates the internal bus hold pullup. When the controller goes into low-power state making the output pins high-impedance, the internal bus hold pullup holds the I/O high, thus avoiding a floating input. The same happens when the external device is drives a logic 0, with the TXE8124-Q1 activating the internal bus hold pulldown. This also makes sure that the TXE8124-Q1 does not generate an interrupt due to noise on the floating inputs, as the device is held in the last known state.

When the bus hold feature is enabled, the external driver must make sure that the current sink or source (indicated by the + or – sign on the specification) due to leakage or other circuits on the board must meet the sustaining or override current. As an example, if the bus hold is activated in high state, then the external devices on the line must not source current from TXE8124-Q1 that exceeds the IBHH(MAX) limit. If the limit is exceeded, the voltage can drop below the VIL(MAX) on the corresponding port pin and trigger the bus-hold pulldown. Similarly, if the bus-hold has to be overridden, then the external devices must be able to sink IBHO(MIN) current from the TXE8124-Q1, to make sure that the device releases the bus-hold.

The software must make sure that the pullup or pulldown selection must not be used along with the bus-hold feature to avoid additional leakage current in the device.