SCPS299B May   2025  – July 2026 TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8124 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TXE8124-Q1 can be reset to the default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 8-2 and Figure 8-3 .

TXE8124-Q1 VCC is Lowered to 0V and Then RAMPED Up Figure 8-2 VCC is Lowered to 0V and Then RAMPED Up
TXE8124-Q1 VCC is Lowered Below the POR Threshold, Then Ramped Back Up Figure 8-3 VCC is Lowered Below the POR Threshold, Then Ramped Back Up

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tVCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 8-4 provides more information on how to measure these specifications.

TXE8124-Q1 Glitch Width and Glitch Height Figure 8-4 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the SPI state machine are initialized to the default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 8-5 provides more detail on this specification.

TXE8124-Q1 VPOR Figure 8-5 VPOR