SCPS299B May   2025  – July 2026 TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8124 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
RESET
tw Reset pulse duration, SDO CLOAD = 100pF (Figure 6-1) 100 ns
tREC Reset recovery time, SDO CLOAD = 100pF (Figure 6-1) 100 ns
tRESET Time to reset, SDO CLOAD = 100pF (Figure 6-1) 80 ns
Power-On Reset
tFT Fall rate (Figure 8-3) (Figure 8-4) 0.1 2000 ms
tRT Rise rate (Figure 8-3) (Figure 8-4) 0.1 2000 ms
tTRR_GND Time to re-ramp (when VCC drops to GND) (Figure 8-3) 1 µs
tTRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50mV) (Figure 8-4) 40 µs
VCC_GH Level that VCC can glitch down to, but not cause a functional disruption when tVCC_GW = 1μs (Figure 8-5) 1.2 V
tVCC_GW Glitch width that does not cause a functional disruption when VCC_GH = 0.5× VCC (Figure 8-5) 10 µs
Fail-safe IO
fsEN Fail-safe IO enable time (100pF load) (Figure 6-2) Ouput High in normal mode and Output Low in fail-safe mode 100 ns
Output Low in normal mode and output high in fail-safe mode 100 ns
Ouput high in normal mode and input in fail safe mode (500Ω pull down load) 70 ns
Output low in normal mode and input in fail-safe mode (500Ω pull down load) 70 ns
fsDIS Fail-safe IO disable time (100pF load) (Figure 6-2) Ouput High in normal mode and Output Low in fail-safe mode 100 ns
Output Low in normal mode and output high in fail-safe mode 100 ns
Input in normal mode and output high in fail-safe mode (500Ω pull down load) 110 ns
Input in normal mode and output low in fail-safe mode (500Ω pull down load) 90  ns
Digital IO
TGW Digital glitch filter width 70 230 ns