SCPS299B May   2025  – July 2026 TXE8124-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8124 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.5.5 SPI Read

The SPI read operation for TXE8124-Q1 is used to retrieve data from a specific register in single read mode as shown in Figure 7-9 or sequential registers in burst mode as shown in Figure 7-10.


TXE8124-Q1 SPI Single Read
Figure 7-9 SPI Single Read

TXE8124-Q1 SPI Burst Read
Figure 7-10 SPI Burst Read

SPI Read Operation Steps:

  1. Drive CS low. This action enables the internal shift register.
  2. Shift 24 bits of data into the device in a MSB first fashion. Data must be stable during the rising edge of SCLK
  3. The MSB bit must be a '1' indicating a read only transfer.
  4. The third data byte is NOP (no operation) which is dummy data byte.
  5. On the SDO pin, the device sends the first 2 bits as 2’b11 (indicating a status segment), followed by 6 bits that are the Bit 5 to 0 of Fault status register. The next 8 bits are all 0s followed by 8-bit current data in the register selected by register pointer.
  6. After the last bit of data is transferred, drive SCLK low if there is no more data to be transferred.
  7. De-assert CS (drive high) to end the read cycle.