SCPS315 April 2025 TCAL9539R
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus controller sends a command byte, which is stored in the control register in the TCAL9539R. The lower bits of this data byte reflect the internal registers (input, output, polarity inversion, or configuration) that are affected. Bit 6 in conjunction with the lower three bits of the Command byte are used to point to the extended features of the device (Agile IO). The command byte is sent only during a write transmission.
Once a new command has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Upon power-up, hardware reset, or software reset, the control register defaults to 00h.
Figure 7-8 Control Register
Bits| CONTROL REGISTER BITS | COMMAND BYTE (HEX) | REGISTER | PROTOCOL | POWER-UP DEFAULT | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00 | Input Port 0 | Read byte | xxxx xxxx |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 01 | Input Port 1 | Read byte | xxxx xxxx |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 02 | Output Port 0 | Read/write byte | 1111 1111 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 03 | Output Port 1 | Read/write byte | 1111 1111 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 04 | Polarity Inversion 0 | Read/write byte | 0000 0000 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 05 | Polarity Inversion 1 | Read/write byte | 0000 0000 |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 06 | Configuration 0 | Read/write byte | 1111 1111 |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 07 | Configuration 1 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | Output Drive Strength 0 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 41 | Output Drive Strength 0 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 42 | Output Drive Strength 1 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 43 | Output drive strength register 1 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 44 | Input latch register 0 | Read/write byte | 0000 0000 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 45 | Input latch register 1 | Read/write byte | 0000 0000 |
0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 46 | Pull-up/pull-down enable register 0 | Read/write byte | 0000 0000 |
0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 47 | pull-up/pull-down enable register 1 | Read/write byte | 0000 0000 |
0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 48 | pull-up/pull-down selection register 0 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 49 | pull-up/pull-down selection register 1 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 4A | Interrupt mask register 0 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 4B | Interrupt mask register 1 | Read/write byte | 1111 1111 |
0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 4C | Interrupt status register 0 | Read byte | 0000 0000 |
0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 4D | Interrupt status register 1 | Read byte | 0000 0000 |
0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 4F | Output port configuration register | Read/write byte | 0000 0000 |