SCPS315 April   2025 TCAL9539R

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 I2C Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Adjustable Output Drive Strength
      3. 7.3.3 Interrupt Output (INT)
      4. 7.3.4 Reset Input (RESET)
      5. 7.3.5 Software Reset Call
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
    6. 7.6 Register Maps
      1. 7.6.1 Device Address
      2. 7.6.2 Control Register and Command Byte
      3. 7.6.3 Register Descriptions
      4. 7.6.4 Bus Transactions
        1. 7.6.4.1 Writes
        2. 7.6.4.2 Reads
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Minimizing ICC When I/Os Control LEDs
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 I2C Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
I2C Bus - Standard Mode
fsclI2C clock frequency0100kHz
tschI2C clock high time4µs
tsclI2C clock low time4.7µs
tspI2C spike time50ns
tsdsI2C serial-data setup time250ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time1000ns
ticfI2C input fall time300ns
tocfI2C output fall time10pF to 400pF bus300ns
tbufI2C bus free time between stop and start4.7µs
tstsI2C start or repeated start condition setup4.7µs
tsthI2C start or repeated start condition hold4µs
tspsI2C stop condition setup4µs
tvd(data)Valid data timeSCL low to SDA output valid3.45µs
tvd(ack)Valid data time of ACK conditionACK signal from SCL low to SDA (out) low3.45µs
CbI2C bus capacitive load400pF
I2C Bus - Fast Mode
fsclI2C clock frequency0400kHz
tschI2C clock high time0.6µs
tsclI2C clock low time1.3µs
tspI2C spike time50ns
tsdsI2C serial-data setup time100ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time20300ns
ticfI2C input fall time20 × (VCC / 5.5V)300ns
tocfI2C output fall time10pF to 400pF bus20 × (VCC / 5.5V)300ns
tbufI2C bus free time between stop and start1.3µs
tstsI2C start or repeated start condition setup0.6µs
tsthI2C start or repeated start condition hold0.6µs
tspsI2C stop condition setup0.6µs
tvd(data)Valid data timeSCL low to SDA output valid0.9µs
tvd(ack)Valid data time of ACK conditionACK signal from SCL low to SDA (out) low0.9µs
CbI2C bus capacitive load400pF
I2C Bus - Fast Mode Plus
fsclI2C clock frequency01000kHz
tschI2C clock high time0.26µs
tsclI2C clock low time0.5µs
tspI2C spike time50ns
tsdsI2C serial-data setup time50ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time120ns
ticfI2C input fall time20 × (VCC / 5.5V)120ns
tocfI2C output fall time10pF to 550pF bus20 × (VCC / 5.5V)120ns
tbufI2C bus free time between stop and start0.5µs
tstsI2C start or repeated start condition setup0.26µs
tsthI2C start or repeated start condition hold0.26µs
tspsI2C stop condition setup0.26µs
tvd(data)Valid data timeSCL low to SDA output valid0.45µs
tvd(ack)Valid data time of ACK conditionACK signal from SCL low to SDA (out) low0.45µs
CbI2C bus capacitive load550pF