SDAA044 September   2025 AM623 , AM625 , AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Overview of AM62x vs AM62Lx
  6. 3 Power Architecture and PMIC Considerations
  7. 4 IO Voltage Domains and Signal Levels
    1. 4.1 Dual-Voltage vs. 1.8V-Only IO Banks
    2. 4.2 Buffer Types and Fail-Safe IOs
  8. 5 Peripheral Interface Changes
    1. 5.1 Memory Interfaces
    2. 5.2 Connectivity
    3. 5.3 Media and Display Interfaces
    4. 5.4 Analog and Other Interfaces
  9. 6 Boot Configuration and Reset Changes
  10. 7 Package and Layout Considerations
    1. 7.1 BGA Package Options
    2. 7.2 Thermal and Power Dissipation
  11. 8 Summary
  12. 9 Terminology and Acronyms
  13. 10References

5.2 Connectivity

Most high-speed connectivity remains the same, but the voltage differences and some feature removals require changes. The Connectivity Interface Differences table highlights interface differences for networking and serial connectivity.

For more detailed information, see the respective AM62x Sitara™ Processors data sheet or AM62Lx Sitara™ Processors data sheet Peripherals section.

Table 5-2 Connectivity Interface Differences
INTERFACE AM62x AM62Lx DESIGN NOTES
Ethernet (RGMII)
  • 1.8V or 3.3V IO
  • Network boot
  • 1.8V IO only
  • No network boot
 For AM62Lx, use 1.8V-capable PHY; remove Ethernet-boot circuitry.
CAN-FD / UART
  • Wake-capable
  • Connected VDDSHV_CANUART (1.8V/3.3V)
  • No wake support
  • No VDDSHV_CANUART
 Verify voltage domain alignment. For AM62Lx, EXT_WAKEUP/EXTINTn for wake.
USB 2.0
  • 2× ports
  • Configurable modes
  • Integrated PHY
  • VBUS monitoring
 N/A
SPI / McASP
  • 4× SPI
  • 3× McASP
  • 4× SPI
  • 3× McASP
 Verify voltage domain alignment.