SDAA044 September   2025 AM623 , AM625 , AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Overview of AM62x vs AM62Lx
  6. 3 Power Architecture and PMIC Considerations
  7. 4 IO Voltage Domains and Signal Levels
    1. 4.1 Dual-Voltage vs. 1.8V-Only IO Banks
    2. 4.2 Buffer Types and Fail-Safe IOs
  8. 5 Peripheral Interface Changes
    1. 5.1 Memory Interfaces
    2. 5.2 Connectivity
    3. 5.3 Media and Display Interfaces
    4. 5.4 Analog and Other Interfaces
  9. 6 Boot Configuration and Reset Changes
  10. 7 Package and Layout Considerations
    1. 7.1 BGA Package Options
    2. 7.2 Thermal and Power Dissipation
  11. 8 Summary
  12. 9 Terminology and Acronyms
  13. 10References

8 Summary

This document summarizes the migration between AM62x and AM62Lx. Choose the device based on performance or features, versus power or BOM targets, then confirm package, pinout, power and thermal implications using the contents of this document and references.

If migrating from AM62x to AM62Lx, expect lower BOM and power. Plan for fewer A53 cores and no GPU, potential changes to display and graphics options, and differences in peripheral counts and boot modes. Validate the single 0.75V core rail, IO bank voltages, and any pinout and package differences. Designers must account for different pinouts, package sizes, and thermal characteristics, and use the AM62Lx Schematic Design Guidelines and Schematic Review Checklist to verify a correct implementation in the updated design.

If migrating from AM62Lx to AM62x, expect higher compute with up to 4× A53 cores, and optional GPU, with broader display and peripheral options. Plan for higher power and thermal budget, possible split core domains (selectable 0.75V/0.85V VDD_CORE with fixed 0.85V VDDR_CORE), and verify package pin availability for DDR, display, and high-speed IO. Designers must account for different pinouts, package sizes, and thermal characteristics, and use the AM62x Schematic Design Guidelines and Review Checklist to verify a correct implementation in the updated design.