SDAA044 September 2025 AM623 , AM625 , AM62L

3 Power Architecture and PMIC Considerations

One of the main differences in power architecture is that AM62Lx uses a single VDD_CORE 0.75V voltage domain and adds an always-on RTC domain to enable RTC-only low power mode. AM62Lx removes the VMON supply monitor pins and integrates an SDIO_LDO to switch SD card IO between 0V, 1.8V, and 3.3V for UHS-I.

AM62x supports VDD_CORE to run at 0.75V or 0.85V. AM62x includes VMON pins for supply monitoring and does not integrate an SDIO_LDO, so UHS-I SD card IO voltage switching is done with external circuitry.

For complete AM62Lx schematics, recommended power sequences, and low-power mode details, see the AM62L Power Supply Implementation application note, and the AM62Lx Processor Family Schematic Design Guidelines and Checklist Power Architecture section. These documents provide PMIC programming recommendation and sequencing diagrams for AM62Lx designs.

For the AM62x family, use the AM62x Processor Family Schematic, Design Guidelines and Review Checklist Processor Power Architecture section for schematic guidance and review, and the Powering the AM62x with the TPS65219 PMIC, for PDN rails, sequencing examples and PMIC settings.

Table 3-1 Power Supply Differences

POWER ASPECT	AM62x	AM62Lx	DESIGN NOTES
Core Voltage Rails	VDD_CORE dual-voltage options 0.75V, or 0.85V VDDR_CORE always 0.85V	All core power rails operate at 0.75V VDDR_CORE internally merged with VDD_CORE	Program AM62Lx PMIC to 0.75V. AM62Lx does not require dedicated supply for VDDR_CORE supply.
IO Supply Rails	6× LVCMOS IO banks that support a fixed 1.8V/3.3V operation 3× SDIO IO banks that support dynamic operating voltage change between 0V, 1.8V, and 3.3V operation All other IO banks only support a fixed 1.8V operation	2× LVCMOS IO banks that support a fixed 1.8V or 3.3V operation 3× SDIO IO banks that support a dynamic operating voltage change between 0V, 1.8V, and 3.3V operation All other IO banks only support a fixed 1.8V operation	AM62Lx power rails associated with SDIO IOs support dynamic voltage change between 1.8V/3.3V, while the AM62x requires external circuitry for the same functionality. See Dual-Voltage vs. 1.8V-Only IO Banks section for more information.
VMON Pins	VMON_3P3_SOC VMON_1P8_SOC VMON_VSYS	VMON pins not supported	If migrating to AM62Lx, remove any schematic connections or circuitry for VMON related pins; use PMIC power-good outputs or internal supervisors to monitor power supplies instead, as recommended in the AM62L Power Supply Implementation application note.
PMIC Low-Power Enable (PMIC_LPM_EN)	Requires an external pull-up resistor to turn on PMIC	No external pull-up needed due to built-in internal pull-up	If migrating to AM62Lx, drop external pull-up resistor; verify PMIC_LPM_EN0 net ties to the PMIC enable pin. For more information, see the AM62L Power Supply Implementation application note.
PMIC Recommendation	TPS65219 (4× LDOs)	TPS65214 (2× LDOs)	For AM62Lx, verify that power sequencing and voltages comply with the AM62Lx Schematic Checklist and AM62L Power Supply Implementatio application note. For AM62x, check AM62x Schematic Checklist and Powering the AM62x with the TPS65219 PMIC application note.
Low-Power Modes	Partial IO support for CAN/GPIO/UART wakeup DeepSleep MCU Only Standby Dynamic frequency scaling for Cortex-A53 Partial IO wake	No support for Partial IO wake for CAN/GPIO/UART DeepSleep Standby Dynamic frequency scaling RTC Only RTC Only + IO + DDR Self-refresh	Only dedicated wake pins (for example, EXT_WAKEUP0/1) can wake from lowest power states; check the Boot Configuration and Reset Changes section for more information.