TXFIFO Configuration

The TLC69699-Q1 has both a transmit and a receive FIFO, the transmit FIFO (TXFIFO) is the data that was received by the SPI peripheral and transmitted by the CCSI controller. Both FIFOs are 16-bit-wide first-in-first-out memory buffers. The FIFOs are used to store data words to full-fill the timing requirements while the data is crossing between the SPI clock domain and CCSI clock domain. When the SPI clock domain runs at a higher frequency than the CCSI clock domain, the TXFIFO stores data already received by the SPI peripheral which has not been transmitted yet by the CCSI controller. A counter (TXFFST) keeps track of the number of words currently stored in the TXFIFO, the maximum TXFFST value can be set to 0x1FF. An example where the SPI peripheral runs at a higher clock frequency than the CCSI controller is depicted in Figure 3-5 , set a lower CCSI frequency than the SPI frequency as long as the FIFO overflow is properly prevented.

TCON can lower the SPI frequency from 8MHz to 5.2MHz now and the TLC69699-Q1 TXFIFO can help further reduce the CCSI frequency to 5MHz or lower, as shown in Figure 3-6 , the bottom waveform is the TCON SPI output at 5.2MHz and the top side is the TLC69699-Q1 CCSI output at 5MHz. A lower CCSI output frequency for TLC69699-Q1 can be set with CCSI_DATA_RATE as long as the FIFO overflow is properly prevented.