The I/O voltage of the TLC696xx-Q1 family is designed to be compatible with both 1.8V and 3.3V voltage to connect to different kinds of host devices (such as a timing controller). For a logic level design of a traditional interface, the logic low voltage must refer to 0.3 × VCC, and the logic high voltage should refer to 0.7 × VCC, and the actual logic high and low value must refer to the real VCC applied to the device. The SIN/CLK_I of the TLC696xx-Q1 family logic low and high level refers to the fixed value for VCC=1.8V, as listed in Table 2-1.

With the fixed threshold, the TLC696xx-Q1 family has a CLK_O duty cycle increase behavior when the VCC voltage equals 3.3V. Figure 2-1 shows the input and output signal for the internal buffer of the first LED driver, the left side is the input signal of the first device and the right side is the output signal. Assume the host device supports to send a 3.3V/50%-duty cycle clock signal, the TLC696xx-Q1 is expected to recognize the logic high until the rising edge reaches VIH_3.3V and recognize the logic low until the falling edge reaches VIL_3.3V, but the TLC696xx-Q1 family recognizes the logic high earlier(∆t1) and recognizes the logic low later((∆t2). The logic-high period for a 50%-duty cycle clock input is recognized as T/2+∆t1+∆t2, so the LED driver regenerates a clock signal with a higher duty compared to the input.

The clock duty cycle increases across the daisy chain, so one of the limits for the maximum cascaded number is the minimum of the CLK_I low time, as shown in The TLC696xx-Q1 family requires a minimum of 18ns CLK_I low time to recognize a valid clock signal. Situations such as these can worsen, such as when the slew rate of the signal is slower, or the signal frequency is higher (T/2 is smaller).

Figure 2-2 shows a 15.6-inch display backlight design example with one FET controller (TLC69610-Q1) and a 43 piece LED driver (TLC69614-Q1) in a single daisy chain to support up to 2730 dimming zones. As shown in Figure 2-2 , when the CCSI clock frequency is 8MHz, the top side is the input of the first device, and the bottom side is the CLK_O of the last device, the duty cycle increases over the daisy chain, where the CLK low time is only 10ns. The CLK_O of the last device in the daisy chain fails to meet the minimum CLK_I low time requirement for proper readback diagnostic operation. The CLK low time of the last six devices all fail to meet the 18ns requirement, which is aligned with the actual LED backlight board bring up status. (The last six devices control the dimming zones in the black area in real LED mapping) in Figure 2-3.