SDAA082 August 2025 TLC69601-Q1 , TLC69604-Q1
3.1 CCSI Control on the CLK_O Duty Cycle and Data Rate
The TLC69699-Q1 offers two options for duty cycle control. Apart from the traditional 50% duty cycle option, the user can also force the CLK_O high-level pulse duration as 50ns. As listed in Table 3-1, with the CCSI_DC_CTRL combined with CCSI_DATA_RATE, the CLKO high-level pulse duration can be decreased from 50% to a lower percentage. So even with CLKO duty accumulation, the low-level pulse duration can be enlarged from the start and the daisy chain device number can be enlarged.
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 6 | CCSI_DC_CTRL | R/W | 0x0 | Duty cycle control for CCSI 0x0 = Duty cycle of CLK_O is 50% except for CCSI_DATA_RATE[3:0] = 4b'1110 (33.33%) and CCSI_DATA_RATE[3:0] = 4b'1100 (40%) 0x1 = CLK_O high level pulse duration is kept at 50ns except for CCSI_DATA_RATE[3:0] = 4b'111X where it is 25ns |
| 5-4 | RESERVED | R/W | 0x0 | Reserved |
| 3-0 | CCSI_DATA_RATE | R/W | 0x0 | Data rate for CCSI 0x0 = 1Mbit/s 0x1 = 1.25Mbit/s 0x2 = 1.43Mbit/s 0x3 = 1.67Mbit/s 0x4 = 2Mbit/s 0x5 = 2.22Mbit/s 0x6 = 2.5Mbit/s 0x7 = 2.86Mbit/s 0x8 = 3.33Mbit/s 0x9 = 4Mbit/s 0xA = 5Mbit/s 0xB = 6.67Mbit/s 0xC = 8Mbit/s 0xD = 10Mbit/s 0xE = 13.33Mbit/s 0xF = 20Mbit/s |
Figure 3-2 shows the test results under 5MHz CCSI data rate when the CLK_O high-level pulse duration is forced as 50ns, which means the first LED driver in the daisy chain can receive an input clock with lower duty cycle. The low-level pulse duration of the last LED driver can reach 85.9ns, which reserves enough margin from the 18ns minimum requirement.
Figure 3-2 CLK_O for TLC69699-Q1 and the
Last LED Driver at CCSI = 5MHz, CLK_O High-Level Pulse Duration= 50ns