SDAA087 September   2025 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Board Design and Layout Guidance
    1. 2.1 General Board Design Guidance
    2. 2.2 Additional Board Design Guidelines for Signal Integrity
    3. 2.3 Design Example
  6. 3Board Design Simulations
    1. 3.1 Board Model Extraction
      1. 3.1.1 IBIS Model Simulations
    2. 3.2 Simulation Setup
  7. 4Summary
  8. 5References

3.2 Simulation Setup

Setup the IBIS simulation with the following steps:

  • Extract S-parameter files for signals on the board.
  • 3D extraction tool is preferrable but not feasible due to run time limitations. If run-time limitations are a concern, use of a 2.5D extraction tool for board signals is permitted.
  • Obtain the SoC IBIS model at TI.com under the product page.
  • Obtain the device IBIS model from the PHY vendor. This IBIS model must include package, RLC model for device.
  • Build up the simulation netlist as shown in a simulator of your choice.
  • Set up the SoC IBIS model, board model, and device IBIS model.
  • Build up the process, voltage, temperature corners that are going to be simulated.
  • Recommended to simulate across all process, voltage, temperature supported by the IBIS model:
    • Typical
    • Minimal
    • Maximal
  • Analyze the results in a waveform analysis tool and use the pass/fail checks from device data sheet specification to assess the quality of results.
Typical System-Level Simulation Setup Figure 3-1 Typical System-Level Simulation Setup