SDAA087 September   2025 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Board Design and Layout Guidance
    1. 2.1 General Board Design Guidance
    2. 2.2 Additional Board Design Guidelines for Signal Integrity
    3. 2.3 Design Example
  6. 3Board Design Simulations
    1. 3.1 Board Model Extraction
      1. 3.1.1 IBIS Model Simulations
    2. 3.2 Simulation Setup
  7. 4Summary
  8. 5References

1 Introduction

This document contains information applicable to board designs and simulation of high-speed parallel interfaces. These interfaces include those which employ LVCMOS I/O buffers. For supported data rates, see the device-specific data manual. This includes interfaces such as Octal Serial Peripheral Interface (OSPI), RGMII (Reduced Gigabit Media-independent Interface) and others. These interfaces are typically implemented with the use of LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor) IO Buffers on respective devices. The high-speed parallel interfaces specifications are governed by the JEDEC standards such as RGMII EIA/JESD 8-6 1995.