The methodology for validating these High-speed parallel interfaces is outlined in this section. Channel simulations using IBIS models and extracted PCB models are exercised with targeted data attack bit patterns to generate signal waveforms and eye diagrams. These results need to be checked for conformity with setup/hold time, slew rate, clock high and low etc., as defined in the device data sheet. Additional checks need to be performed for ring back with respect to VIH/VIL voltage levels.