SDAA087 September   2025 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Board Design and Layout Guidance
    1. 2.1 General Board Design Guidance
    2. 2.2 Additional Board Design Guidelines for Signal Integrity
    3. 2.3 Design Example
  6. 3Board Design Simulations
    1. 3.1 Board Model Extraction
      1. 3.1.1 IBIS Model Simulations
    2. 3.2 Simulation Setup
  7. 4Summary
  8. 5References

2.3 Design Example

This section offers some guidance for a board design to improve signal quality:

Cload represents the total capacitive load of the peripheral (Package, IO, and so on).

For Cload of approximately 2pF:

Option 1: Keep trace length very short (around 0.5 inch -0.6 inch), add a small resistor (use 10Ω or 22Ω) inserted in the middle of the trace.

Option 2: If trace length cannot be reduced to the 0.5 inch length, and trace length is between one inch and five inches, try the following options.

  • Inserting the resistor in the middle of the trace as in option 1
  • Adding a small lumped capacitor (use different values 1pF, 2pF, 3pF, and so on) close to the PHY BGA.

Option 3: If Option 1 and 2 are not feasible, increase trace length to the maximum allowable by the PHY spec (six inches) Adding a small lumped capacitor similar to option 2b can also be used in addition to increased trace length.

Note that these are possible suggestions to help improve signal quality. Option 1 is expected to provide the best overall signal quality but the customer must simulate and evaluate which of these options works best for a specific system.