SDAA475 August   2026 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   1
  2.    Abstract
  3.    Trademarks
  4. 1 Introduction
  5. 2USB 3.1 Compliance Mode: Theory of Operation
    1. 2.1 Acronyms and Definitions
    2. 2.2 LTSSM and RX Detect
    3. 2.3 Compliance Mode Entry Methods
    4. 2.4 Register Reference
      1. 2.4.1 xHCI PORTSC: Port Status and Control Register
      2. 2.4.2 PORTSC Bit-Field Description (USB 3.0 — xHCI Spec §4.19.7)
      3. 2.4.3 PLS Encoding: USB 3.0 Link States
      4. 2.4.4 Verifying RX Detect Before Compliance Entry
      5. 2.4.5 Compliance Write Value Decode: 0x0a010340
    5. 2.5 Compliance Pattern CP1 and SSC
      1. 2.5.1 USB PHY Register — CP1 ( Clock Pattern)
      2. 2.5.2 Register Address
      3. 2.5.3 CP1 Write Value Decode: 0x18230c10
  6. 3 Compliance Procedure — TDA4VH/AH/TDA4AP/VP
    1. 3.1  Hardware Requirements
    2. 3.2  Software Requirements
    3. 3.3  EVM Setup
    4. 3.4  Compliance Pattern Reference
    5. 3.5  LFPS: Low-Frequency Periodic Signaling
    6. 3.6  Compliance Pattern 0 (CP0)
    7. 3.7  Compliance Pattern 1 (CP1)
    8. 3.8  LeCroy Scope Setup and Results
    9. 3.9  Troubleshooting
    10. 3.10 Compliance Procedure: DRA821 / TDA4AL/VL/VE / J721S2
  7. 4 Summary
  8. 5References

2.5.1 USB PHY Register — CP1 ( Clock Pattern)

This USB PHY register write instructs the analog TX block to output the CP1 compliance pattern. The register must be written after the PORTSC compliance write.