1. Resistor Divider and Capacitor Approach

   For signal voltage over 200V or 400V, it is difficult to find a preferred buffer amplifier with high voltage and low leakage and high bandwidth. Many times, two resistor divider with parallel capacitors are designed for converting high voltage to low voltage to fit ADC input range. it is very effective, has relatively small current leakage, simple circuit and small layout area if divider resistors and capacitors value are not too high and very accurately. Following Figure 2-5 is a simulation which uses resistors and capacitors divider in ultra-high voltage sensing. It is drawed in TINA-TI simulation tool which is downloaded from TI.com.

   Figure 2-5 RC Divider Sensing Simulation Circuit

   Assume input 200V step with max 200mA output capability(R_internal=1K ohm), resistor and capacitor are ideal, and there is not parasitic parameter in layout and trace. From simlation result, everything looks perfect especially for very small settling time (Figure 2-6), but it has 20uA current leakage and converting output accuracy is not good because different signal sources have different internal resistance.

   Figure 2-6 RC Divider Simulation Result

   If considering capacitor and layout are not ideal, let's say C1 total capacitance vary from 6pF to 14pF, we will see settling time (Figure 2-7) is different and max is near 0.5ms, and sometimes overshoot is very big which means need reserve enough input margin for ADC and lost ADC resolution.

   Figure 2-7 Various C1 Simulation

   Too small C1 value is much affected by parasitic parameters of components and layout and air. Proportionally increase C1 and C2 value to keep away from these effects. Assume C1=100pF and C2=9.9nF , let's say C1=100pF and C2=9.9nF, both have 5% tolerance which include components tolerance and layout parasitic parameter, vary C1 from 95pF to 105pF, the max settling time is near 5ms shown in Figure 2-8.

   Figure 2-8 Increase C1 C2 and Various C1 Simulation

   With these simulations, resistor and capacitor divider sensing approach maybe suitable for precision instruments development, each channel needs fine tuning very carefully. It is not suitable for thousands of channel design for ATE system.

2. Isolated Buffer Sensing Approach

   Figure 2-9 is isolated sensing topology, "buffer" becomes an isolated circuit.

   Figure 2-9 Isolated Buffer Sensing Topology

   The isolated buffer circuit can accept input signal with very small current leakage and its output have high current driving capability. It will not be affected by capacitors or layout parasitic parameters. Only concern is placement area is a bit big. Following Figure 2-10 is simulation circuit. in this circuit Mosfet can take 490V span such as ±245V or -100V to 390V signal converting.

   From simulation result Figure 2-11, Settling time is around 5us from -100 to 390V input to stable signal output.

   Figure 2-10 Isolated Buffer Simulation Circuit
   Figure 2-11 Isolated Buffer Settling Time

   As Figure 2-12 shown, when start signal 0V, leakage is around 2.5pA, it takes about 10us that current leakage is less than 10pA after input steps up to 390V from 0V. it takes about 12us that current leakage is less than 10pA after input steps down to -100V from 390V

   Figure 2-12 Isolated Buffer Current Leakage
3. Floating signal chain approach

It's ok for Isolated buffer sensing approach to take high voltage converting task. But if sensing small current with high common mode voltage, CMRR noise causes a significant reduction for current sensing accuracy. Another issue is it is difficult to find very high voltage P-Mosfet. So, when voltage is over 1000V or 3000V, floating topology is a better choice. Figure 2-13 shows a typical floating signal chain topology.

Figure 2-13 Floating Signal Chain

Floating signal chain approach is putting all digital components and signal chain on high voltage side. That will make current sensing common voltage near 0-volt. A low voltage precision amplifier can be used to buffer high output voltage. TIDA-010962 is designed with this topology to implement four quadrant VI sources. With this topology it achieves nearly 20ppm accuracy and fast measurement performance. It also supports Buffer mode to measure external high voltage such as high voltage digital multimeter. For detail schematic and performance, you can search TIDA-010962 in TI.com