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  1.   Abstract
  2.   Trademarks
  3. 1Introduction: MSP Sigma-Delta ADCs and Common Applications
  4. 2MSP Sigma-Delta ADC Portfolio
  5. 3Sigma-Delta ADC Overview
  6. 4MSP Sigma-Delta ADC Features
    1. 4.1  ADC Inputs: Differential or Single-Ended
    2. 4.2  Input Channels: Independent or Multiplexed
    3. 4.3  Integrated Buffers
    4. 4.4  Integrated PGAs
    5. 4.5  Offset Calibration: Internal or External
    6. 4.6  Voltage Reference: Internal or External
    7. 4.7  ADC Modulator Clock Frequency: Fixed or Adjustable
    8. 4.8  Sampling Rate versus Data Rate
    9. 4.9  Conversion Mode: Single or Continuous
    10. 4.10 Groups of ADC Channels
    11. 4.11 Preload
    12. 4.12 Output Format: Unipolar or Bipolar Data
    13. 4.13 Module Synchronization
    14. 4.14 Architecture: Discrete-Time versus Continuous-Time
  7. 5Solutions to Common MSP Sigma-Delta ADC Configuration Issues
    1. 5.1 ADC Input Configuration
      1. 5.1.1 Settling Time Exceeds Recommended Minimum
      2. 5.1.2 Amplitude of the Input Signal Exceeds FSR
      3. 5.1.3 Missing Anti-Aliasing Filters
    2. 5.2 ADC Clocking Configuration
      1. 5.2.1 Incorrect Sampling Frequency
    3. 5.3 ADC Results
      1. 5.3.1 Unexpected Output Data Format
      2. 5.3.2 Low Resolution
      3. 5.3.3 Data Interpretation
    4. 5.4 Reference Module (REF) Configuration
      1. 5.4.1 Choosing Between an Internal or External Reference
      2. 5.4.2 Connecting the Recommended Capacitors
      3. 5.4.3 Delaying Conversions Until the Reference Settles
    5. 5.5 Hardware Recommendations
  8. 6Frequently Asked Questions
  9. 7References

3 Sigma-Delta ADC Overview

Analog-to-digital converters do just that: they convert real-world signals into an abstract representation for digital processing. There are several different ADC architectures including slope, pipeline, SAR and SD. Each architecture has its advantages and disadvantages. For example, SAR ADCs typically support higher throughput but lower resolution than SD ADCs. Also, SD ADCs support negative input voltages whereas most SAR ADCs do not. While this application report focuses on SD ADCs, watch Part 1 of the Choosing the Best ADC Architecture for Your Application training series to learn more about different ADC architectures.

A typical Sigma-Delta (also referred to as Delta-Sigma) ADC is shown in Figure 3-1 and includes two main components: the modulator and the decimation filter. At a high level, the modulator functions as the analog front end that samples the analog input signal and then converts it into a modulated digital bit stream which gets fed into the decimation filter. The decimation filter includes a digital filter that converts the bit stream into an oversampled digital representation of the analog signal and a decimator that undersamples that result to produce the digital output.

GUID-20200922-CA0I-B4WD-QWBS-MHT2ZHSWWGQ3-low.gif Figure 3-1 Typical Sigma-Delta ADC Block Diagram

To learn more about how SD ADCs work, watch Part 3 and Part 4 of the Choosing the Best ADC Architecture for Your Application training series. Also, see the device-specific data sheet and user's guide.