SLAAE29B January   2023  – August 2026 MSPM0C1105 , MSPM0C1106 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Concepts
    2. 1.2 Goals of Cybersecurity
    3. 1.3 Platform Security Enablers
  5. 2Device Security Model
    1. 2.1 Device Identity
    2. 2.2 Initial Conditions at Boot
    3. 2.3 Boot Configuration Routine (BCR)
    4. 2.4 Bootstrap Loader (BSL)
    5. 2.5 Boot Flow
    6. 2.6 User-Specified Security Policies
      1. 2.6.1 Boot Configuration Routine (BCR) Policies
        1. 2.6.1.1 Serial Wire Debug Related Policies
          1. 2.6.1.1.1 SWD Security Level 0
          2. 2.6.1.1.2 SWD Security Level 1
          3. 2.6.1.1.3 SWD Security Level 2
        2. 2.6.1.2 Bootstrap Loader (BSL) Enable/Disable Policy
        3. 2.6.1.3 Flash Memory Protection and Integrity Related Policies
          1. 2.6.1.3.1 Locking the Application (MAIN) Flash Memory
          2. 2.6.1.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 2.6.1.3.3 Verifying Integrity of Application (MAIN) Flash Memory
        4. 2.6.1.4 Bootstrap Loader (BSL) Security Policies
          1. 2.6.1.4.1 BSL Access Password
          2. 2.6.1.4.2 BSL Read-out Policy
          3. 2.6.1.4.3 BSL Security Alert Policy
      2. 2.6.2 Customer Secure Code (CSC) Security Policies
        1. 2.6.2.1 CSC Enforced Bankswap
        2. 2.6.2.2 CSC Enforced Firewalls
        3. 2.6.2.3 CSC Key Write to KEYSTORE
      3. 2.6.3 Configuration Data Error Resistance
        1. 2.6.3.1 CRC-Backed Configuration Data
        2. 2.6.3.2 16-bit Pattern Match for Critical Fields
  6. 3Secure Boot
    1. 3.1 Secure Processing Environment Isolation
    2. 3.2 Customer Secure Code (CSC)
      1. 3.2.1 Secure Boot Flow
      2. 3.2.2 Flash Memory Map
      3. 3.2.3 Features
        1. 3.2.3.1 CMAC Acceleration
        2. 3.2.3.2 Asymmetric Verification
        3. 3.2.3.3 KEYSTORE and Firewall
        4. 3.2.3.4 CSC Performance
      4. 3.2.4 Quick Start Guide
        1. 3.2.4.1 Environment Setup
        2. 3.2.4.2 Step by Step Guidance
        3. 3.2.4.3 CSC NONMAIN Configuration
        4. 3.2.4.4 Customize Changes on CSC Example
    3. 3.3 Boot Image Manager (BIM)
      1. 3.3.1 Secure Boot Flow
      2. 3.3.2 Flash Memory Map
      3. 3.3.3 Quick Start Guide
  7. 4Secure Storage
    1. 4.1 Flash Write Protection
    2. 4.2 Flash Read-Execute Protection
    3. 4.3 Flash IP Protection
    4. 4.4 Data Bank Protection
    5. 4.5 Secure Key Storage
    6. 4.6 SRAM Protection
    7. 4.7 Hardware Monotonic Counter
  8. 5Cryptographic Acceleration
    1. 5.1 Hardware AES Acceleration
      1. 5.1.1 AES
      2. 5.1.2 AESADV
    2. 5.2 Hardware True Random Number Generator (TRNG)
  9. 6FAQ
  10. 7Summary
  11. 8References
  12. 9Revision History

1.3 Platform Security Enablers

The security enablers included in MSPM0 devices are given inTable 1-2. The debug security features andmain flash memory integrity verification feature could be found in NONMAIN Layout Types and NONMAIN Registers sections in device series technical reference manual. And the secure boot, secure storage and cryptographic accelerators features could be found in device specific datasheet.

Table 1-2 MSPM0 MCU Platform Security Enablers
Security EnablerDevice FeatureM0C1103/4M0C1105/6M0L1x0x/M0L134xM0G110xM0G3x0x/M0G150xM0H321xM0L111xM0L211xM0Lx22xM0G511xM0G321xM0Gx51x
Debugging securityPassword authenticated debug accessHashedYesYesYesHashedHashedHashedHashedHashedHashedHashed
Password authenticated bootstrap loader accessNo ROM BSLNo ROM BSLYesYesYesNo ROM BSLHashedHashedHashedHashedHashedHashed
Password authenticated main flash memory mass eraseHashedYesYesYesHashedHashedHashedHashedHashedHashedHashed
Password authenticated complete factory resetHashedYesYesYesHashedHashedHashedHashedHashedHashedHashed
TI failure analysis (FA) enable/disableYesYesYesYesYesYesYesYesYesYesYes
Complete hardware disable of serial wire debug (SWD) interfaceYesYesYesYesYesYesYesYesYesYesYesYes
Permanently lockable device configuration dataYesYesYesYesYesYesYesYesYesYesYesYes
Error resistant device configuration dataYesYesYesYesYesYesYesYesYesYesYes
Passwords are stored in hashed form only (SHA2-256)YesYesYesYesYesYesYesYes
Secure bootCSC ExistsYesYesYesYesYesYesYesYes
Permanently lockable main flash memoryYesYesYesYesYesYesYesYesYesYesYesYes
CRC-32 verified main flash regionYesYesYesYesYesYesYesYesYesYesYes
SHA2-256 verified main flash memory regionYesYesYesYesYesYesYesYes
Single point of entry to main flash application at bootYesYesYesYesYesYesYesYesYesYesYesYes
Asymmetric firmware image authentication routines (ECDSA with P-256, SHA2-256 based on software)YesYesYesYesYesYesYesYesYesYesYes
Symmetric firmware image authentication routines (AES-CMAC based on hardware)YesYesYesYesYesYes
Lockable flash for ECDSA public key revocation and rollback protectionYesYesYesYesYesYesYesYes
SRAM write-execute mutual exclusion (W^X) boundaryYesYesYesYesYesYesYesYesYesYesYes
Secure StorageFlash write protection firewallYesYesYesYesYesYesYesYes
Flash read/execute (RX) protection firewallYesYesYesYesYesYesYesYes
Flash IP protection area (execute only, no read access)YesYesYesYesYesYesYesYes
Flash bank write-execute mutual exclusion (W^X)YesYesYesYesYes
Data bank write read protectionYesYesYes
Key storeYesYesYesYesYesYes
Hardware monotonic counterYesYesYesYes
Cryptographic accelerationTrue random number generator (TRNG) with self-testYesYesYesYes
Basic AES accelerator (without GCM/CMAC/GHASH support)YesYesYesYesYesYesYes
Advanced AES accelerator (with GCM/CMAC/GHASH support)YesYesYesYesYesYes
Device identityUnique device identifier (96-bit)YesYesYesYesYesYesYesYesYesYesYesYes

Certifications

ARM PSA Level

L1

Planned

L1

Planned

L1

Planned

L1

L1

Planned

L1

Planned

L1

Planned
EVITA capabilityEVITA-LightEVITA-LightEVITA-LightEVITA-LightEVITA-LightEVITA-LightEVITA-Light
ISO 21434 process compliantPlannedPlannedPlannedPlannedPlanned
Attack Resistance Analysis3P firmware vulnerability analysisYesYesYesYesYesYesYes
Boot configuration routine fault injection attack countermeasuresYesYesYesYesYesYesYes