SLAAER9 May   2025 TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Recording Path Mixers
    1. 2.1 Main ASI Mixer
      1. 2.1.1 Q-31 Formatting for Mixer Coefficients
      2. 2.1.2 Recording Path Main ASI Mixer: Example
    2. 2.2 Auxiliary ASI Mixer
      1. 2.2.1 Recording Path Auxiliary ASI Mixer - Example
    3. 2.3 ADC-to-DAC Loopback Mixer
    4. 2.4 TDM Transmission on DOUT
  6. 3Playback Path Mixers
    1. 3.1 Main ASI Mixer
      1. 3.1.1 Q-16 Formatting for Mixer Coefficients
      2. 3.1.2 Playback Path Main ASI Mixer - Example
    2. 3.2 Auxiliary ASI Mixer
      1. 3.2.1 Playback Path Auxiliary ASI Mixer - Example
    3. 3.3 Playback Path Side-Chain Mixer
      1. 3.3.1 Playback Path Side-Chain - Example
  7. 4Application: ADC Channel Summation to Improve TAC5212 Dynamic Range
  8. 5Application: Analog Input to Analog Output Signal Flow in TAC5412-Q1
  9. 6Summary
  10. 7References

Application: Analog Input to Analog Output Signal Flow in TAC5412-Q1

In the TAC5412-Q1 devices, the analog input can be mixed along with the DAC signal chain and played onto the analog outputs through the digital mixers. This is done using the ADC-to-DAC loopback path, and the side-chain mixer to translate the analog input voltage to a corresponding analog output voltage. Figure 5-2shows the analog input and analog output connections:


 Input and Output Connections for
          TAC5412-Q1

Figure 5-1 Input and Output Connections for TAC5412-Q1

This was tested on a TAC5412Q15B5EVM-K evaluation module using the following script where the ADC path is configured for a 10Vrms full-scale differential input, and the DAC path is configured for a 2Vrms full-scale differential output. The expectation here can be that when a 8.91Vrms (-1dBFS for ADC) is provided at the INxP/M pins, a 1.78Vrms (-1dBFS for DAC) can be seen on the corresponding OUTxP/M pins. The measurements are shown in Figure 5-2.

w a0 00 00 # Page 0 
w a0 01 01 #SW Reset
d 01
# Page 0 Register Writes
w a0 00 00
w a0 02 09 #Exit Sleep Mode with DREG and VREF Enabled
d 10
w a0 1a 30 #PASI in TDM protocol with 32-bit word length
w a0 4d 00 #VREF set to 2.75V for 2Vrms differential fullscale input
w a0 50 00 #ADC Channel 1 configured for differential input with 10Vrms swing
w a0 55 00 #ADC Channel 2 configured for differential input with 10Vrms swing
w a0 64 20 #DAC Channel 1 configured for differential output with 0.6*Vref as common mode
w a0 65 20 #DAC OUT1P configured for line out driver and audio bandwidth
w a0 66 20 #DAC OUT1M configured for line out driver and audio bandwidth
w a0 6b 20 #DAC Channel 2 configured for differential output with 0.6*Vref as common mode
w a0 6c 20 #DAC OUT2P configured for line out driver and audio bandwidth
w a0 6d 20 #DAC OUT2M configured for line out driver and audio bandwidth

w a0 26 01 #RX Offset = 1

w a0 28 20 #RX CH1 to DAC CH1
w a0 29 21 #RX CH2 to DAC CH2

#ADC INPUTS
#CH1 = 1kHz, 8.91Vrms Sine (-1dBFS)
#CH2 = 2.2kHz, 5Vrms Sine (-6dBFS)
#ADC Loopback mixers
#LB1 = 1*CH1 + 0*CH2
w a0 00 0a #Page 10
w a0 48 7f ff ff ff #a1 = 1
w a0 4c 00 00 00 00 #b1 = 0
w a0 50 00 00 00 00 #c1 = 0
w a0 54 00 00 00 00 #d1 = 0

#LB2 = 0*CH1 + 1*CH2
w a0 58 00 00 00 00 #a2 = 0
w a0 5c 7f ff ff ff #b2 = 1
w a0 60 00 00 00 00 #c2 = 0
w a0 64 00 00 00 00 #d2 = 0

#DAC Inputs
#CH1 = CH2 = 0

w a0 00 11 #Page 17
#DAC output OUT1 = 1*LB1
#DAC output OUT2 = 1*LB2
w a0 58 00 00 3f ff #a1 = 0, a2 = 0
w a0 5c 00 00 00 00 #a3 = 0, a4 = 0
w a0 60 3f ff 00 00 #b1 = 0, b2 = 0
w a0 64 00 00 00 00 #b3 = 0, b4 = 0
w a0 68 00 00 00 00 #c1 = 0, c2 = 0
w a0 6c 00 00 00 00 #c3 = 0, c4 = 0
w a0 70 00 00 00 00 #d1 = 0, d2 = 0
w a0 74 00 00 00 00 #d3 = 0, d4 = 0


w a0 00 00 #Page 0
w a0 76 cc #ADC CH1-2, DAC CH1-2 Enabled
w a0 78 e0 #ADC, DAC Path and MICBIAS enabled
 Analog Input-to-Analog Output Measured
          on TAC5412-Q1 Figure 5-2 Analog Input-to-Analog Output Measured on TAC5412-Q1