SLAAET8A April   2025  – December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

4.1.1 POR and BOR

A power-on reset (POR) circuit indicates that the external supply has reached sufficient voltage to start the on-chip bandgap reference and BOR circuit. A user-programmable brownout reset (BOR) circuit makes sure that the external supply is maintained at a sufficient voltage to support correct operation of the device. In terms of EMS, the presence of the POR and BOR makes the MCU more robust. This also makes sure that if any outside disturbance affects the power supply, then the application can recover safely.

When the supply voltage (VDD) drops below POR-, the entire device state is cleared. Small variations in VDD that do not pass below the BOR0- threshold do not cause a BOR- violation, and the device continues to run. Behavior for BORx thresholds other than BOR0 (for example, BOR1-BOR3) is the same as shown for BOR0, except the BOR circuit is configured to generate an interrupt rather than immediately triggering a BOR reset.

POR, BOR vs. Supply Voltage (VDD) Figure 4-1 POR, BOR vs. Supply Voltage (VDD)

There are four selectable BOR threshold levels (BOR0-BOR3). During startup, the BOR threshold is always BOR0. After booting up, the software can reconfigure the BOR to use a higher threshold level (BOR1-BOR3). When the BOR threshold is BOR0, the violation generates a BOR reset. When the BOR threshold is reconfigured to BOR1, BOR2, or BOR3, the BOR generates a SYSCTL interrupt instead. This can be used to give the application an early warning that the supply has dropped below a certain level. Users can save the data and choose to reset the device in the interrupt service routine. To enable this functions, follow the instructions in Figure 4-2.

BOR Level Setting in SysConfig Figure 4-2 BOR Level Setting in SysConfig