SLASEG6C May   2018  â€“ September 2025 TAS3251

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Amplifier Electrical Characteristics
    6. 6.6  DAC Electrical Characteristics
    7. 6.7  Audio Characteristics (BTL)
    8. 6.8  Audio Characteristics (PBTL)
    9. 6.9  MCLK Timing
    10. 6.10 Serial Audio Port Timing – Target Mode
    11. 6.11 Serial Audio Port Timing – Controller Mode
    12. 6.12 I2C Bus Timing –Standard
    13. 6.13 I2C Bus Timing –Fast
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
      1. 6.15.1 BTL Configuration
      2. 6.15.2 PBTL Configuration
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-on-Reset (POR) Function
      2. 7.3.2  Enable Device
      3. 7.3.3  DAC and DSP Clocking
        1. 7.3.3.1 Internal Clock Error Notification (CLKE)
      4. 7.3.4  Serial Audio Port
        1. 7.3.4.1 Clock Controller Mode from Audio Rate Controller Clock
        2. 7.3.4.2 Clock Target Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        3. 7.3.4.3 Clock Target Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 7.3.4.3.1 Clock Generation Using the PLL
          2. 7.3.4.3.2 PLL Calculation
            1. 7.3.4.3.2.1 Examples:
        4. 7.3.4.4 Serial Audio Port – Data Formats and Bit Depths
          1. 7.3.4.4.1 Data Formats and Controller or Target Modes of Operation
        5. 7.3.4.5 Input Signal Sensing (Power-Save Mode)
      5. 7.3.5  Volume Control
        1. 7.3.5.1 DAC Digital Gain Control
          1. 7.3.5.1.1 Emergency Volume Ramp Down
      6. 7.3.6  SDOUT Port and Hardware Control Pin
      7. 7.3.7  I2C Communication Port
        1. 7.3.7.1 Target Address
        2. 7.3.7.2 Register Address Auto-Increment Mode
        3. 7.3.7.3 Packet Protocol
        4. 7.3.7.4 Write Register
        5. 7.3.7.5 Read Register
        6. 7.3.7.6 DSP Book, Page, and Register Update
          1. 7.3.7.6.1 Book and Page Change
          2. 7.3.7.6.2 Swap Flag
          3. 7.3.7.6.3 Example Use
      8. 7.3.8  Pop and Click Free Startup and Shutdown
      9. 7.3.9  Integrated Oscillator for Output Power Stage
        1. 7.3.9.1 Oscillator Synchronization and Target Mode
      10. 7.3.10 Device Output Stage Protection System
        1. 7.3.10.1 Error Reporting
        2. 7.3.10.2 Overload and Short Circuit Current Protection
        3. 7.3.10.3 Signal Clipping and Pulse Injector
        4. 7.3.10.4 DC Speaker Protection
        5. 7.3.10.5 Pin-to-Pin Short Circuit Protection (PPSC)
        6. 7.3.10.6 Overtemperature Protection OTW and OTE
        7. 7.3.10.7 Undervoltage Protection (UVP) and Power-on Reset (POR)
        8. 7.3.10.8 Fault Handling
        9. 7.3.10.9 Output Power Stage Reset
      11. 7.3.11 Initialization, Startup and Shutdown
        1. 7.3.11.1 Power Up and Startup Sequence
        2. 7.3.11.2 Power Down and Shutdown Sequence
        3. 7.3.11.3 Device Mute
        4. 7.3.11.4 Device Unmute
        5. 7.3.11.5 Device Reset
        6. 7.3.11.6 Mute with DAC_MUTE or Clock Error
          1. 7.3.11.6.1 Mute using DAC_MUTE
        7. 7.3.11.7 Mute using Serial Audio Port Clock
        8. 7.3.11.8 Muting before an Unplanned Shutdown with DAC_MUTE
        9. 7.3.11.9 Output Power Stage Startup Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Audio Port Operating Modes
        1. 7.4.1.1 Controller and Target Mode Clocking for Digital Serial Audio Port
      2. 7.4.2 Communication Port Operating Modes
      3. 7.4.3 Speaker Amplifier Operating Modes
        1. 7.4.3.1 Stereo Mode
        2. 7.4.3.2 Mono Mode
    5. 7.5 Programming
      1. 7.5.1 Audio Processing Features
      2. 7.5.2 Processing Block Description
        1. 7.5.2.1  Input Scale and Mixer
          1. 7.5.2.1.1 Example
        2. 7.5.2.2  Sample Rate Converter
        3. 7.5.2.3  Parametric Equalizers (PEQ)
        4. 7.5.2.4  BQ Gain Scale
        5. 7.5.2.5  Dynamic Parametric Equalizer (DPEQ)
        6. 7.5.2.6  Two-Band Dynamic Range Control
        7. 7.5.2.7  Automatic Gain Limiter
          1. 7.5.2.7.1 Softening Filter Alpha (AEA)
          2. 7.5.2.7.2 Softening Filter Omega (AEO)
          3. 7.5.2.7.3 Attack Rate
          4. 7.5.2.7.4 Release Rate
          5. 7.5.2.7.5 Attack Threshold
        8. 7.5.2.8  Fine Volume
        9. 7.5.2.9  THD Boost
        10. 7.5.2.10 Level Meter
      3. 7.5.3 Other Processing Block Features
        1. 7.5.3.1 Number Format
          1. 7.5.3.1.1 Coefficient Format Conversion
      4. 7.5.4 Checksum
        1. 7.5.4.1 Cyclic Redundancy Check (CRC) Checksum
        2. 7.5.4.2 Exclusive or (XOR) Checksum
    6. 7.6 Register Maps
      1. 7.6.1 Registers - Page 0
        1. 7.6.1.1  Register 1 (0x01)
        2. 7.6.1.2  Register 2 (0x02)
        3. 7.6.1.3  Register 3 (0x03)
        4. 7.6.1.4  Register 4 (0x04)
        5. 7.6.1.5  Register 6 (0x06)
        6. 7.6.1.6  Register 7 (0x07)
        7. 7.6.1.7  Register 8 (0x08)
        8. 7.6.1.8  Register 9 (0x09)
        9. 7.6.1.9  Register 12 (0x0C)
        10. 7.6.1.10 Register 13 (0x0D)
        11. 7.6.1.11 Register 14 (0x0E)
        12. 7.6.1.12 Register 15 (0x0F)
        13. 7.6.1.13 Register 16 (0x10)
        14. 7.6.1.14 Register 17 (0x11)
        15. 7.6.1.15 Register 18 (0x12)
        16. 7.6.1.16 Register 20 (0x14)
        17. 7.6.1.17 Register 21 (0x15)
        18. 7.6.1.18 Register 22 (0x16)
        19. 7.6.1.19 Register 23 (0x17)
        20. 7.6.1.20 Register 24 (0x18)
        21. 7.6.1.21 Register 27 (0x1B)
        22. 7.6.1.22 Register 28 (0x1C)
        23. 7.6.1.23 Register 29 (0x1D)
        24. 7.6.1.24 Register 30 (0x1E)
        25. 7.6.1.25 Register 32 (0x20)
        26. 7.6.1.26 Register 33 (0x21)
        27. 7.6.1.27 Register 34 (0x22)
        28. 7.6.1.28 Register 37 (0x25)
        29. 7.6.1.29 Register 40 (0x28)
        30. 7.6.1.30 Register 41 (0x29)
        31. 7.6.1.31 Register 42 (0x2A)
        32. 7.6.1.32 Register 43 (0x2B)
        33. 7.6.1.33 Register 44 (0x2C)
        34. 7.6.1.34 Register 59 (0x3B)
        35. 7.6.1.35 Register 60 (0x3C)
        36. 7.6.1.36 Register 61 (0x3D)
        37. 7.6.1.37 Register 62 (0x3E)
        38. 7.6.1.38 Register 63 (0x3F)
        39. 7.6.1.39 Register 64 (0x40)
        40. 7.6.1.40 Register 65 (0x41)
        41. 7.6.1.41 Register 67 (0x43)
        42. 7.6.1.42 Register 68 (0x44)
        43. 7.6.1.43 Register 69 (0x45)
        44. 7.6.1.44 Register 70 (0x46)
        45. 7.6.1.45 Register 71 (0x47)
        46. 7.6.1.46 Register 72 (0x48)
        47. 7.6.1.47 Register 73 (0x49)
        48. 7.6.1.48 Register 74 (0x4A)
        49. 7.6.1.49 Register 75 (0x4B)
        50. 7.6.1.50 Register 76 (0x4C)
        51. 7.6.1.51 Register 78 (0x4E)
        52. 7.6.1.52 Register 79 (0x4F)
        53. 7.6.1.53 Register 85 (0x55)
        54. 7.6.1.54 Register 86 (0x56)
        55. 7.6.1.55 Register 87 (0x57)
        56. 7.6.1.56 Register 88 (0x58)
        57. 7.6.1.57 Register 91 (0x5B)
        58. 7.6.1.58 Register 92 (0x5C)
        59. 7.6.1.59 Register 93 (0x5D)
        60. 7.6.1.60 Register 94 (0x5E)
        61. 7.6.1.61 Register 95 (0x5F)
        62. 7.6.1.62 Register 108 (0x6C)
        63. 7.6.1.63 Register 119 (0x77)
        64. 7.6.1.64 Register 120 (0x78)
      2. 7.6.2 Registers - Page 1
        1. 7.6.2.1 Register 1 (0x01)
        2. 7.6.2.2 Register 2 (0x02)
        3. 7.6.2.3 Register 6 (0x06)
        4. 7.6.2.4 Register 7 (0x07)
        5. 7.6.2.5 Register 9 (0x09)
  9. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 Stereo, Bridge Tied Load (BTL) Application
      2. 8.1.2 Mono, Parallel Bridge-Tied Load (PBTL) Application
        1. 8.1.2.1 Parallel Bridge-Tied Load (PBTL), Pre-Filter
        2. 8.1.2.2 Parallel Bridge-Tied Load, Post-Filter
      3. 8.1.3 Design Requirements
      4. 8.1.4 Detailed Design Procedure
        1. 8.1.4.1 Step One: Schematic and Layout Design
          1. 8.1.4.1.1 Decoupling Capacitor Recommendations
          2. 8.1.4.1.2 PVDD Capacitor Recommendations
          3. 8.1.4.1.3 BST Capacitors
          4. 8.1.4.1.4 Heatsink
        2. 8.1.4.2 Step Two: Configure the Fixed-Function Process Flow for Use with the Target System
        3. 8.1.4.3 Step Three: Software Integration
      5. 8.1.5 Two TAS3251 Device Configurations
        1. 8.1.5.1 2 x PBTL Application
        2. 8.1.5.2 2 x BTL + 1 x PBTL Application
      6. 8.1.6 Three or More TAS3251 Device Configurations
      7. 8.1.7 Application Curves
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Power Supplies
        1. 8.2.1.1 DAC_DVDD and DAC_AVDD Supplies
          1. 8.2.1.1.1 CPVSS, CN and CP Charge Pump
        2. 8.2.1.2 VDD Supply
        3. 8.2.1.3 GVDD_X Supply
        4. 8.2.1.4 PVDD Supply
        5. 8.2.1.5 BST Supply
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 General Guidelines for TAS3251
        2. 8.3.1.2 Importance of PVDD Bypass Capacitor Placement
      2. 8.3.2 Layout Examples
        1. 8.3.2.1 Bridge-Tied Load (BTL) Layout Example
        2. 8.3.2.2 Parallel Bridge-Tied Load (PBTL), Pre-Filter
        3. 8.3.2.3 Parallel Bridge-Tied Load (PBTL), Post-Filter
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.3.4.3.2.1 Examples:
  • If K = 8.5, then J = 8, D = 5000
  • If K = 7.12, then J = 7, D = 1200
  • If K = 14.03, then J = 14, D = 0300
  • If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

  • 1MHz ≤ ( PLLCKIN / P ) ≤ 20MHz
  • 64MHz ≤ (PLLCKIN x K x R / P ) ≤ 100MHz
  • 1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

  • 6.667MHz ≤ PLLCLKIN / P ≤ 20MHz
  • 64MHz ≤ (PLLCKIN x K x R / P ) ≤ 100MHz
  • 4 ≤ J ≤ 11
  • R = 1

When the PLL is enabled,

  • fS = (PLLCLKIN × K × R) / (2048 × P)
  • The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12MHz and fS = 44.1kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12MHz and fS = 48kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 7-3.

Table 7-3 PLL Registers
DIVIDER FUNCTION BITS
PLLE PLL enable P0-R4, [0]
PPDV PLL P P0-R20, [3:0]
PJDV PLL J P0-R21, [5:0]
PDDV PLL D P0-R22, [5:0]
P0-R23, [7:0]
PRDV PLL R P0-R24, [3:0]
Table 7-4 PLL Configuration Recommendations
EQUATIONS DESCRIPTION
fS (kHz) Sampling frequency
RMCLK Ratio between sampling frequency and MCLK frequency (MCLK frequency = RMCLK x sampling frequency)
MCLK (MHz) System controller clock frequency at MCLK input (pin 20)
PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 7-2
P One of the PLL coefficients in Equation 1
PLL REF (MHz) Internal reference clock frequency which is produced by MCLK / P
M = K × R The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D One of the PLL coefficients in Equation 1
R One of the PLL coefficients in Equation 1
PLL fS Ratio between fS and PLL VCO frequency (PLL VCO / fS)
DSP fS Ratio between operating clock rate and fS (PLL fS / NMAC)
NMAC The clock divider value in Table 7-2
DSP CLK (MHz) The operating frequency as DSPCK in Figure 7-2
MOD fS Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
MOD f (kHz) DAC operating frequency as DACCK in
NDAC DAC clock divider value in Table 7-2
DOSR OSR clock divider value in Table 7-2 for generating OSRCK in Figure 7-2. DOSR must be chosen so that MOD fS / DOSR = 16 for correct operation.
NCP NCP (negative charge pump) clock divider value in Table 7-2
CP f Negative charge pump clock frequency (fS × MOD fS / NCP)
% Error Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
  • This value is typically zero but can be non-zero especially when K is not an integer (D is not zero).
  • This value can be non-zero only when the TAS3251 device acts as a controller.

The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL. Table 7-5 provides for easy reference to the recommended clock divider settings for the PLL as a Controller Clock.

Table 7-5 Recommended Clock Divider Settings for PLL as Controller Clock
fS
(kHz)		RMCLKMCLK
(MHz)		PLL VCO
(MHz)		PPLL REF
(MHz)		M = K×RK = J×DRPLL fSDSP fSNMACDSP CLK
(MHz)		MOD fSMOD f
(kHz)		NDACDOSR% ERRORNCPCP f
(kHz)
81281.02498.30411.02496482122881024128.19276861441648041536
1921.53698.30411.53664322122881024128.19276861441648041536
2562.04898.30412.04848481122881024128.19276861441648041536
3843.07298.30431.02496482122881024128.19276861441648041536
5124.09698.30431.36572362122881024128.19276861441648041536
7686.14498.30432.04848481122881024128.19276861441648041536
10248.19298.30432.73136361122881024128.19276861441648041536
11529.21698.30491.02496482122881024128.19276861441648041536
153612.28898.30491.36572362122881024128.19276861441648041536
204816.38498.30491.8254541122881024128.19276861441648041536
307224.57698.30492.73136361122881024128.19276861441648041536
11.0251281.411290.316811.4116432281921024811.28965125644.81632041411.2
1922.116890.316830.70612832481921024811.28965125644.81632041411.2
2562.822490.316812.8223232181921024811.28965125644.81632041411.2
3844.233690.316831.4116432281921024811.28965125644.81632041411.2
5125.644890.316831.8824848181921024811.28965125644.81632041411.2
7688.467290.316832.8223232181921024811.28965125644.81632041411.2
102411.289690.316833.7632424181921024811.28965125644.81632041411.2
115212.700890.316891.4116432281921024811.28965125644.81632041411.2
153616.934490.316891.8824848181921024811.28965125644.81632041411.2
204822.579290.316892.5093636181921024811.28965125644.81632041411.2
307233.868890.316893.7632424181921024811.28965125644.81632041411.2
16641.02498.30411.0249648261441024616.38438461441624041536
1282.04898.30412.0484848161441024616.38438461441624041536
1923.07298.30413.0723232161441024616.38438461441624041536
2564.09698.30414.0962424161441024616.38438461441624041536
3846.14498.30432.0484848161441024616.38438461441624041536
5128.19298.30432.7313636161441024616.38438461441624041536
76812.28898.30434.0962424161441024616.38438461441624041536
102416.38498.30435.4611818161441024616.38438461441624041536
115218.43298.30436.1441616161441024616.38438461441624041536
153624.57698.30492.7313636161441024616.38438461441624041536
204832.76898.30493.6412727161441024616.38438461441624041536
307249.15298.30495.4611818161441024616.38438461441624041536
22.05641.411290.316811.4116432240961024422.57922565644.81616041411.2
1282.822490.316812.8223232140961024422.57922565644.81616041411.2
1924.233690.316831.4116432240961024422.57922565644.81616041411.2
2565.644890.316815.6451616140961024422.57922565644.81616041411.2
3848.467290.316832.8223232140961024422.57922565644.81616041411.2
51211.289690.316833.7632424140961024422.57922565644.81616041411.2
76816.934490.316835.6451616140961024422.57922565644.81616041411.2
102422.579290.316837.5261212140961024422.57922565644.81616041411.2
115225.401690.316892.8223232140961024422.57922565644.81616041411.2
153633.868890.316893.7632424140961024422.57922565644.81616041411.2
204845.158490.316895.0181818140961024422.57922565644.81616041411.2
32321.02498.30411.0249648230721024332.76819261441612041536
481.53698.30411.5366416430721024332.76819261441612041536
642.04898.30412.0484824230721024332.76819261441612041536
1284.09698.30414.0962424130721024332.76819261441612041536
1926.14498.30432.0484848130721024332.76819261441612041536
2568.19298.30424.0962424130721024332.76819261441612041536
38412.28898.30434.0962424130721024332.76819261441612041536
51216.38498.30435.4611818130721024332.76819261441612041536
76824.57698.30438.1921212130721024332.76819261441612041536
102432.76898.304310.92399130721024332.76819261441612041536
115236.86498.30494.0962424130721024332.76819261441612041536
153649.15298.30468.1921212130721024332.76819261441612041536
44.1321.411290.316811.4116432220481024245.15841285644.8168041411.2
642.822490.316812.8223216220481024245.15841285644.8168041411.2
1285.644890.316815.6451616120481024245.15841285644.8168041411.2
1928.467290.316832.8223232120481024245.15841285644.8168041411.2
25611.289690.316825.6451616120481024245.15841285644.8168041411.2
38416.934490.316835.6451616120481024245.15841285644.8168041411.2
51222.579290.316837.5261212120481024245.15841285644.8168041411.2
76833.868890.3168311.2988120481024245.15841285644.8168041411.2
102445.158490.3168315.05366120481024245.15841285644.8168041411.2
48321.53698.30411.5366432220481024249.1521286144168041536
643.07298.30413.0723216220481024249.1521286144168041536
1286.14498.30416.1441616120481024249.1521286144168041536
1929.21698.30433.0723232120481024249.1521286144168041536
25612.28898.30426.1441616120481024249.1521286144168041536
38418.43298.30436.1441616120481024249.1521286144168041536
51224.57698.30438.1921212120481024249.1521286144168041536
76836.86498.304312.28888120481024249.1521286144168041536
102449.15298.304316.38466120481024249.1521286144168041536
96323.07298.30413.072321621024512249.152646144164041536
484.60898.30431.536643221024512249.152646144164041536
646.14498.30416.14416821024512249.152646144164041536
12812.28898.30426.144161611024512249.152646144164041536
19218.43298.30436.144161611024512249.152646144164041536
25624.57698.30446.144161611024512249.152646144164041536
38436.86498.30466.144161611024512249.152646144164041536
51249.15298.30486.144161611024512249.152646144164041536