at
TA = 25°C, PVDD = VDD = IOVDD = 1.8V, external or internal VREFIO =
1.25V, RLOAD = 50kΩ to GND, CLOAD = 100pF to GND, and
digital inputs at IOVDD or GND (unless otherwise noted)
Figure 5-3 DAC
DNL vs Digital Input Code
Figure 5-5 DAC
INL vs Digital Input Code
Figure 5-7 MIN
and MAX DAC DNL Range vs Temperature
Figure 5-9 DAC
TUE vs Digital Input Code
Figure 5-11 MIN
and MAX DAC TUE vs Temperature
Figure 5-13 DAC
Source and Sink Current Capability
Figure 5-15 DAC Gain Error vs Temperature
Figure 5-17 DAC Full Scale Error vs Temperature
Figure 5-19 DAC
Output Noise, 0.1Hz to 10Hz
Figure 5-21 DAC
Settling Time vs Load (Rising Voltage Step)
Figure 5-23 DAC
Settling Time With Linear Slew Rate Control
Figure 5-25 DAC
Glitch Impulse Rising Edge
Figure 5-27 DAC
Supply Power On, PVDD = 1.8V
| 1: 0.4V to 2V range,
midcode |
3: 0.3V to 2.2V
range, |
| 2: 0.2V to 1V
range, midcode |
zero code |
Figure 5-29 DAC
PVDD Supply Collapse Response, RANGE = 1
| 0.15V
to 1.25V range, midcode |
|
Figure 5-31 DAC
VDD Supply Collapse Response,
RANGE = 0
Figure 5-33 DAC
Output Voltage Long-Term Stability
Figure 5-4 DAC
DNL vs Digital Input Code
Figure 5-6 DAC
INL vs Digital Input Code
Figure 5-8 MIN
and MAX DAC INL Range vs Temperature
Figure 5-10 DAC
TUE vs Digital Input Code
Figure 5-12 DAC
RESET Response
Figure 5-14 DAC
Source and Sink Current Capability
Figure 5-16 DAC Offset Error vs Temperature
Figure 5-18 DAC Zero Scale Error vs Temperature
Figure 5-20 DAC
Output Noise Density vs Frequency
Figure 5-22 DAC
Settling Time vs Load (Falling Voltage Step)
Figure 5-24 DAC
Settling Time With Sinusoidal Slew Rate Control
Figure 5-26 DAC
Glitch Impulse Falling Edge
Figure 5-28 DAC
Supply Power On, PVDD = 3.3V
| 0.15V
to 1.25V range, midcode |
|
Figure 5-30 DAC
PVDD Supply Collapse Response, RANGE = 0
| 0.4V
to 2V range, midcode |
|
Figure 5-32 DAC
IOVDD Supply Collapse Response, RANGE = 1
Figure 5-34 DAC AC PSRR vs Frequency