SLASFB7A November   2024  – August 2025 TAS5802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Supplies
      2. 6.3.2 Device Clocking
      3. 6.3.3 Serial Audio Port – Clock Rates
      4. 6.3.4 Serial Audio Port (SAP)
      5. 6.3.5 Digital Audio Processing
      6. 6.3.6 Class D Audio Amplifier
        1. 6.3.6.1 Speaker Amplifier Gain Select
    4. 6.4 Device Functional Modes
      1. 6.4.1 Software Control
      2. 6.4.2 Speaker Amplifier Operating Modes
        1. 6.4.2.1 BTL Mode
      3. 6.4.3 Low EMI Modes
        1. 6.4.3.1 Spread Spectrum
        2. 6.4.3.2 Channel to Channel Phase Shift
        3. 6.4.3.3 Multi-Devices PWM Phase Synchronization
      4. 6.4.4 Thermal Foldback
      5. 6.4.5 Device State Control
      6. 6.4.6 Device Modulation
        1. 6.4.6.1 BD Modulation
        2. 6.4.6.2 1SPW Modulation
        3. 6.4.6.3 Hybrid Modulation
    5. 6.5 Programming and Control
      1. 6.5.1 I2C Serial Communication Bus
      2. 6.5.2 Target Address
        1. 6.5.2.1 Random Write
        2. 6.5.2.2 Sequential Write
        3. 6.5.2.3 Random Read
        4. 6.5.2.4 Sequential Read
        5. 6.5.2.5 DSP Memory Book, Page and BQ update
        6. 6.5.2.6 Checksum
          1. 6.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 6.5.2.6.2 Exclusive or (XOR) Checksum
      3. 6.5.3 Control via Software
        1. 6.5.3.1 Startup Procedures
        2. 6.5.3.2 Shutdown Procedures
        3. 6.5.3.3 Protection and Monitoring
          1. 6.5.3.3.1 Overcurrent Shutdown (OCSD)
          2. 6.5.3.3.2 DC Detect
          3. 6.5.3.3.3 Device Over Temperature Protection
          4. 6.5.3.3.4 Over Voltage Protection
          5. 6.5.3.3.5 Under Voltage Protection
          6. 6.5.3.3.6 Clock Fault
  9. 7 Register Maps
    1. 7.1 CONTROL PORT Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bootstrap Capacitors
      2. 8.1.2 Inductor Selections
      3. 8.1.3 Power Supply Decoupling
      4. 8.1.4 Output EMI Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 2.0 (Stereo BTL) System
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedures
          1. 8.2.1.2.1 Step 1: Hardware Integration
          2. 8.2.1.2.2 Step 2: Speaker Tuning
          3. 8.2.1.2.3 Step 3: Software Integration
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 DVDD Supply
      2. 8.3.2 PVDD Supply
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 General Guidelines for Audio Amplifiers
        2. 8.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 8.4.1.3 Optimizing Thermal Performance
          1. 8.4.1.3.1 Device, Copper, and Component Layout
          2. 8.4.1.3.2 Stencil Pattern
            1. 8.4.1.3.2.1 PCB footprint and Via Arrangement
            2. 8.4.1.3.2.2 Solder Stencil
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information
    3. 11.2 Mechanical Data

6.3.4 Serial Audio Port (SAP)

The serial audio interface port is a 3-wire serial port with the signals LRCK/FS, SCK, and SDIN. SCK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio interface. Serial data is clocked into the device on the rising edge of SCK. The LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified, and TDM/DSP data. Data formats are selected via Register (SAP_CTRL1 Register (Offset = 33h) [Reset = 02h] - D[5:4]). If the high width of LRCK/FS in TDM/DSP mode is less than 8 cycles of SCK, the register (SAP_CTRL1 Register (Offset = 33h) [Reset = 02h] - D[3:2]) should be set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word length, and clock rate supported by this device are shown in Table 1. The data formats are detailed in Figure 1 through Figure 6. The word length are selected via Register (SAP_CTRL1 Register (Offset = 33h) [Reset = 02h] - D[1:0]). The offsets of data are selected via Register ( SAP_CTRL1 Register (Offset = 33h) [Reset = 02h] - D[7]) and Register (SAP_CTRL2 Register (Offset = 34h) [Reset = 00h] - D[7:0]). The default setting is I2S and 24-bit word length.

Table 6-2 Audio Data Formats, Word Lengths, and Clock Rates
FORMATDATA BITSLRCK/FS FREQUENCY (kHz)SCK RATE (fs)
I2S/LJ/RJ32, 24, 20, 1616, 32, 44.1/48, 9632,64
TDM/DSP32, 24, 20, 1616, 32, 44.1/48, 96128, 256, 512
TAS5802 Left Justified Audio Data FormatFigure 6-2 Left Justified Audio Data Format
TAS5802 I2S Audio Data Format
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 6-3 I2S Audio Data Format
TAS5802 Right Justified Audio Data Format
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 6-4 Right Justified Audio Data Format
TAS5802 TDM Audio Data Format
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 6-5 TDM Audio Data Format
TAS5802 TDM 2 Audio Data Format
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 6-6 TDM 2 Audio Data Format

The I2S target timing is shown in Figure 6-7.

TAS5802 Serial Audio Timing - TargetFigure 6-7 Serial Audio Timing - Target
TAS5802 I2C Communication Timing - Target Figure 6-8 I2C Communication Timing - Target