SLASFB9 June   2025 MSPM0H3216

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2.     9
    3. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
    4. 6.3 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3   Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 High Frequency Crystal/Clock
      4. 7.9.4 Low Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 ADC
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
      3. 7.11.3 Linearity Parameters
      4. 7.11.4 Typical Connection Diagram
    12. 7.12 Temperature Sensor
    13. 7.13 VREF
      1. 7.13.1 Voltage Characteristics
      2. 7.13.2 Electrical Characteristics
    14. 7.14 I2C
      1. 7.14.1 I2C Characteristics
      2. 7.14.2 I2C Filter
      3. 7.14.3 I2C Timing Diagram
    15. 7.15 SPI
      1. 7.15.1 SPI
      2. 7.15.2 SPI Timing Diagram
    16. 7.16 UART
    17. 7.17 TIMx
    18. 7.18 Windowed Watchdog Characteristics
    19. 7.19 Emulation and Debug
      1. 7.19.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0H321x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA_B
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 SPI
    19. 8.19 I2C
    20. 8.20 Low-Frequency Sub System (LFSS)
    21. 8.21 RTC_B
    22. 8.22 IWDT_B
    23. 8.23 WWDT
    24. 8.24 Timers (TIMx)
    25. 8.25 Device Analog Connections
    26. 8.26 Input/Output Diagrams
    27. 8.27 Serial Wire Debug Interface
    28. 8.28 Device Factory Constants
    29. 8.29 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.11.1 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vin(ADC) Analog input voltage range(1) Applies to all ADC analog input pins 0 VDD V
VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V
VR+ sourced from internal reference (VREF) 4.05 V
VR- Negative ADC reference voltage 0 V
Fs ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.6 Msps
RES = 0x1 (10-bit mode), External Reference 1.77
RES = 0x2 (8-bit mode), External Reference 2
FS ADC sampling frequency RES = 0x0 (12-bit mode), Internal Reference 0.9 Msps
RES = 0x1 (10-bit mode), Internal Reference 1
RES = 0x2 (8-bit mode), Internal Reference 1.2
I(ADC) Operating supply current
into VDD terminal		 FS = 1.6MSPS, VR+ = VDD 350 μA
FS = 0.9MSPS,VR+ = VREF = 4.05V  (VREF power consumption included) 400
CS/H ADC sample-and-hold capacitance 0.22 pF
Rin ADC switch resistance 15 kΩ
ENOBDC Effective number of bits, DC External reference (2) 11 bit
ENOBDC Effective number of bits, DC External reference with over sampling 12.4 bit
ENOBDC Effective number of bits, DC Internal reference, VR+ = VREF = 4.05V 10.3 bit
ENOBAC Effective number of bits, AC External reference with over sampling,  fin = 1kHz 11.4 bit
ENOBAC Effective number of bits, AC External reference(2), fin = 5kHz 10.7 bit
ENOBAC Effective number of bits, AC Internal reference, VR+ = VREF = 4.05V,  fin = 5kHz 10.2 bit
SNR Signal-to-noise ratio External reference (2) 68 dB
External reference with over sampling 74
Internal reference, VR+ = VREF = 4.05V  64
PSRRDC Power supply rejection ratio, DC VDD = VDD(min) to VDD(max)
Internal reference, VR+ = VREF = 4.05V 		 61 dB
PSRRDC Power supply rejection ratio, DC External reference (4), VDD = VDD(min) to VDD(max) 61 dB
PSRRAC Power supply rejection ratio, AC ΔVDD = 0.1 V at 1 kHz
Internal reference, VR+ = VREF = 4.05V		 48.6 dB
PSRRAC Power supply rejection ratio, AC ΔVDD = 0.1 V at 1 kHz
External reference, VR+ = VREF = 4.05V		 61 dB
Twakeup ADC Wakeup Time Assumes internal reference is active 5 us
VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor (3) -1.5 +1.5 %
ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 16 uA
(1) The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results.
(2) All external reference specifications are measured with VR+ = VREF+ = VDD = 5V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin
(3) Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3.