The CPU subsystem (MCPUSS) implements an Arm
Cortex-M0+ CPU, an instruction prefetch and cache,
a system timer, a memory protection unit, and
interrupt management features. The Arm Cortex-M0+
is a cost-optimized 32-bit CPU that delivers high
performance and low power to embedded
applications. Key features of the CPU Sub System
include:
- Arm Cortex-M0+ CPU supports clock frequencies from 32kHz to 32MHz
- ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction
- Single-cycle access to GPIO registers through Arm single-cycle IO port
- Prefetch logic to improve sequential code execution, and I-cache with 2 64-bit cache lines
- System timer (SysTick) with 24-bit down counter and automatic reload
- Memory protection unit (MPU) with 8
programmable regions
- Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chaining
- Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency