SLASFC9A December   2024  – June 2025 MSPM0L1116 , MSPM0L1117

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 Low Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 I2C
      1. 7.15.1 I2C Characteristics
      2. 7.15.2 I2C Filter
      3. 7.15.3 I2C Timing Diagram
    16. 7.16 SPI
      1. 7.16.1 SPI
      2. 7.16.2 SPI Timing Diagram
    17. 7.17 UART
    18. 7.18 TIMx
    19. 7.19 TRNG Electrical Characteristics
    20. 7.20 TRNG Switching Characteristics
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 Security
    17. 8.17 TRNG
    18. 8.18 AESADV
    19. 8.19 Keystore
    20. 8.20 CRC-P
    21. 8.21 UART
    22. 8.22 I2C
    23. 8.23 SPI
    24. 8.24 Low-Frequency Sub System (LFSS)
    25. 8.25 RTC_B
    26. 8.26 IWDT_B
    27. 8.27 WWDT
    28. 8.28 Timers (TIMx)
    29. 8.29 Device Analog Connections
    30. 8.30 Input/Output Diagrams
    31. 8.31 Serial Wire Debug Interface
    32. 8.32 Bootstrap Loader (BSL)
    33. 8.33 Device Factory Constants
    34. 8.34 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.9.3 Low Frequency Crystal/Clock

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low frequency crystal oscillator (LFXT)
fLFXT LFXT frequency 32768 Hz
DCLFXT LFXT duty cycle 30 70 %
OALFXT LFXT crystal oscillation allowance 419 kΩ
CL, eff Integrated effective load capacitance(1) 1 pF
tstart, LFXT LFXT start-up time 1000 ms
ILFXT LFXT current consumption XT1DRIVE=0, LOWCAP=1 200 nA
Low frequency digital clock input (LFCLK_IN)
fLFIN LFCLK_IN frequency (2) SETUSEEXLF=1 29491 32768 36045 Hz
DCLFIN LFCLK_IN duty cycle (2) SETUSEEXLF=1 40 60 %
LFCLK Monitor
fFAULTLF LFCLK monitor fault frequency (3) MONITOR=1 2800 4200 8400 Hz
(1) This includes parasitic bond and package capacitance (≈2pF per pin), calculated as CLFXIN×CLFXOUT/(CLFXIN+CLFXOUT), where CLFXIN and CLFXOUT are the total capacitance at LFXIN and LFXOUT, respectively.
(2) The digital clock input (LFCLK_IN) accepts a logic level square wave clock.
(3) The LFCLK monitor may be used to monitor the LFXT or LFCLK_IN.  It will always fault below the MIN fault frequency, and will never fault above the MAX fault frequency.