The following table describes the functions
available on every pin for each device package.
Note: Each digital I/O on a device is mapped to a
specific Pin Control Management Register (PINCMx) that lets users configure the desired
Pin Function using the PINCM.PF control bits.
The IOMUX only supports
connecting one IOMUX-managed digital function to the pin at the same time. The PINCM.PF and
PINCM.PC in
Section 8.12 are recommended to be set to
0 when non-IOMUX managed functions (such as analog connections) are intended to be used on a
pin. However, non-IOMUX managed signals (such as analog inputs and WAKE inputs) can be enabled
on a pin at the same time that an IOMUX managed digital function is enabled on the pin,
provided there is no contention between the functions. In this case, the designer must verify
that no contention exists between the functions enabled on each pin.
Table 6-1 Digital IO Features by IO Type| IO STRUCTURE | INVERSION CONTROL | DRIVE STRENGTH CONTROL | HYSTERESIS CONTROL | PULLUP RESISTOR | PULLDOWN RESISTOR | WAKEUP LOGIC |
|---|
| SDIO (Standard drive) | Y | | | Y | Y | |
| SDIO (Standard drive) with wake(1) | Y | | | Y | Y | Y |
HDIO (High drive) | Y | Y | | Y | Y | Y |
| HSIO (High speed) | Y | Y | | Y | Y | |
| ODIO (5V-tolerant open drain) | Y | | Y | | Y | Y |