SLAU887 February   2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview of BSL Features
  4. 2Terminology
  5. 3BSL Architecture
    1. 3.1 Design
      1. 3.1.1 Timeout Feature
        1. 3.1.1.1 Interface Autodetection
        2. 3.1.1.2 Command Reception
    2. 3.2 BSL Invocation
      1. 3.2.1 Blank Device
      2. 3.2.2 Application Request
      3. 3.2.3 GPIO Based Invocation
      4. 3.2.4 Debug Mailbox Command
      5. 3.2.5 Others
        1. 3.2.5.1 Pre-Boot Application Verification
    3. 3.3 Memory
      1. 3.3.1 SRAM Memory Usage
    4. 3.4 BSL Configuration
    5. 3.5 BSL Status
  6. 4Bootloader Protocol
    1. 4.1 Packet Format
    2. 4.2 UART and I2C BSL Protocol
      1. 4.2.1 BSL Acknowledgment
      2. 4.2.2 Peripheral Configuration
        1. 4.2.2.1 UART
        2. 4.2.2.2 I2C
        3. 4.2.2.3 CRC
    3. 4.3 Bootloader Core Commands
      1. 4.3.1  Connection
      2. 4.3.2  Get Device Info
      3. 4.3.3  Unlock Bootloader
      4. 4.3.4  Program Data
      5. 4.3.5  Program Data Fast
      6. 4.3.6  Readback Data
      7. 4.3.7  Flash Range Erase
      8. 4.3.8  Mass Erase
      9. 4.3.9  Factory Reset
      10. 4.3.10 Standalone Verification
      11. 4.3.11 Start Application
      12. 4.3.12 Change Baud Rate
    4. 4.4 BSL Core Response
      1. 4.4.1 BSL Core Message
      2. 4.4.2 Detailed Error
      3. 4.4.3 Memory Readback
      4. 4.4.4 Device Info
      5. 4.4.5 Standalone Verification
    5. 4.5 Bootloader Security
      1. 4.5.1 Password Protected Commands
        1. 4.5.1.1 Security Alert
      2. 4.5.2 BSL Entry
  7. 5Sample Program Flow with Bootloader
  8. 6Secondary Bootloader
    1. 6.1 Secondary Bootloader Example
  9. 7Interface Plug-in
    1. 7.1 Implementation
      1. 7.1.1 Init
      2. 7.1.2 Receive
      3. 7.1.3 Transmit
      4. 7.1.4 Deinit
      5. 7.1.5 Important Notes
    2. 7.2 Flash Plug-in Type
    3. 7.3 Overriding an Existing Interface
      1. 7.3.1 UART Interface Flash Plug-in Example
  10. 8References
  11. 9Revision History

4.3.4 Program Data

Structure

Header

Length

CMD

Address

Data

CRC32

0x80

L1

L2

0x20

A1...A4

D1...Dn

C1

C2

C3

C4

Description

The program command is used to write the data D1 through Dn in the memory address starting from A1...A4. This command performs the blocking write. Once the programming is done a Message response is sent to Host.

Programming is allowed to Main flash (application memory), Non-main Flash (configuration memory) and SRAM memory. For details on the absolute address range please refer to the device specific data sheet.

Flash memory should be erased by the Host before programming. See Flash range erase, Mass erase for more details on erasing the Main flash region. Non-main flash can only be erased by the Factory reset command.

Due to the Flash controller characteristic, the start address and Length of the data should be 8 byte aligned for flash programming.

Note:

SRAM memory is not fully accessible by the Host. See GUID-20221116-SR0T-CR07-GX5T-K8FLKCTN1ZBQ.html for more details.

Protected

Yes

Address

Start address of the memory region to be programmed. A1...A4, where A1 is the Least Significant Byte of the 32 bit address.

Data

Data bytes to be written in the specified address. Maximum size of the data that can be sent is limited by the Buffer size of the device. Buffer size is known from Get Device Info command .

Command Returns

BSL Acknowledgment and BSL core response with Message about the Status of the operation. See section GUID-20221116-SR0T-5XQF-V5HX-0PC5JLS5BBJ2.html for more details.

Example

Host: 80 0D 00 20 00 00 00 00 00 00 00 04 00 00 00 08 7A DC AE B8

BSL: 00 08 02 00 3B 00 38 02 94 82