SLDS204D October   2014  – February 2025 PGA300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Reverse Voltage Protection
    6. 5.6  Electrical Characteristics: Regulators
    7. 5.7  Electrical Characteristics: Internal References
    8. 5.8  Electrical Characteristics: Bridge Sensor Supply
    9. 5.9  Electrical Characteristics: External Temperature Sensor Supply
    10. 5.10 Electrical Characteristics: Internal Temperature Sensor
    11. 5.11 Electrical Characteristics: P Gain Stage (Chopper Stabilized)
    12. 5.12 Electrical Characteristics: P Analog-to-Digital Converter
    13. 5.13 Electrical Characteristics: T Gain Stage (Chopper Stabilized)
    14. 5.14 Electrical Characteristics: T Analog-to-Digital Converter
    15. 5.15 Electrical Characteristics: DAC Output
    16. 5.16 Electrical Characteristics: DAC Gain Stage
    17. 5.17 Electrical Characteristics: Diagnostics
    18. 5.18 Electrical Characteristics: One-Wire Interface
    19. 5.19 Electrical Characteristics: EEPROM (Non-Volatile Memory)
    20. 5.20 Electrical Characteristics: Power-Supply Currents
    21. 5.21 Electrical Characteristics: Timing
    22. 5.22 Electrical Characteristics: Accuracy
    23. 5.23 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reverse-Voltage Protection Circuit
      2. 6.3.2  Linear Regulators
      3. 6.3.3  Internal References
        1. 6.3.3.1 High-Voltage Reference
        2. 6.3.3.2 Accurate Reference
      4. 6.3.4  Bridge Sensor Supply for Resistive Bridges (BRG+ to BRG–)
      5. 6.3.5  ITEMP Supply for External Temperature Sensors
      6. 6.3.6  Internal Temperature Sensor
      7. 6.3.7  Pressure Measurement Signal Chain
        1. 6.3.7.1 P Gain Stage
        2. 6.3.7.2 P Analog-to-Digital Converter
          1. 6.3.7.2.1 P Sigma-Delta Modulator for P ADC
          2. 6.3.7.2.2 P Decimation Filter for P ADC
      8. 6.3.8  Temperature Measurement Signal Chain
        1. 6.3.8.1 T Gain Stage
        2. 6.3.8.2 T Analog-to-Digital Converter
          1. 6.3.8.2.1 T Sigma-Delta Modulator for T ADC
          2. 6.3.8.2.2 T Decimation Filters for T ADC
      9. 6.3.9  DAC Output
        1. 6.3.9.1 Ratiometric vs Absolute Output Mode
      10. 6.3.10 DAC Gain Stage
      11. 6.3.11 Digital Compensation and Filter
        1. 6.3.11.1 Digital Gain and Offset Compensation
        2. 6.3.11.2 Temperature and Nonlinearity Compensation
          1. 6.3.11.2.1 Operating Without TC and NL Compensation
          2. 6.3.11.2.2 Temperature Compensation Using the Internal Temperature Sensor
        3. 6.3.11.3 Clamping
        4. 6.3.11.4 Digital IIR Filter
          1. 6.3.11.4.1 Filter Coefficients
            1. 6.3.11.4.1.1 No Filtering
            2. 6.3.11.4.1.2 Filter Coefficients for P ADC Sampling Rate = 128 µs
      12. 6.3.12 Diagnostics
        1. 6.3.12.1 Power-Supply Diagnostics
        2. 6.3.12.2 Signal Chain Diagnostics
          1. 6.3.12.2.1 P Gain and T Gain Input Diagnostics
          2. 6.3.12.2.2 P Gain and T Gain Output Diagnostics
          3. 6.3.12.2.3 Masking Signal Chain Diagnostics
        3. 6.3.12.3 Fault Detection Timing
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operating Modes
        1. 6.4.1.1 Execution Mode
        2. 6.4.1.2 Configuration Mode
      2. 6.4.2 Output Modes
        1. 6.4.2.1 Voltage Output Mode
        2. 6.4.2.2 Current Output Mode
    5. 6.5 Programming
      1. 6.5.1 One-Wire Interface (OWI)
        1. 6.5.1.1 Overview of OWI
        2. 6.5.1.2 Activating and Deactivating the OWI
          1. 6.5.1.2.1 Activating OWI Communication
          2. 6.5.1.2.2 Deactivating OWI Communication
        3. 6.5.1.3 OWI Protocol
          1. 6.5.1.3.1 OWI Frame Structure
            1. 6.5.1.3.1.1 Standard Field Structure
            2. 6.5.1.3.1.2 Frame Structure
            3. 6.5.1.3.1.3 Sync Field
            4. 6.5.1.3.1.4 Command Field
            5. 6.5.1.3.1.5 Data Fields
          2. 6.5.1.3.2 OWI Commands
            1. 6.5.1.3.2.1 OWI Write Command
            2. 6.5.1.3.2.2 OWI Read-Initialization Command
            3. 6.5.1.3.2.3 OWI Read-Response Command
            4. 6.5.1.3.2.4 OWI EEPROM Cache Burst-Write Command
            5. 6.5.1.3.2.5 OWI EEPROM Cache Burst-Read Command
          3. 6.5.1.3.3 OWI Operations
            1. 6.5.1.3.3.1 Write Operation
            2. 6.5.1.3.3.2 Read Operation
            3. 6.5.1.3.3.3 EEPROM Cache Burst Write
            4. 6.5.1.3.3.4 EEPROM Cache Burst Read
      2. 6.5.2 Memory
        1. 6.5.2.1 EEPROM Memory
          1. 6.5.2.1.1 EEPROM Cache
          2. 6.5.2.1.2 EEPROM Programming Procedure
          3. 6.5.2.1.3 EEPROM Programming Current
          4. 6.5.2.1.4 EEPROM Memory Map CRC
      3. 6.5.3 Control and Status Registers
  8. 7 Register Maps
    1. 7.1 Register Settings
    2. 7.2 Control and Status Registers
    3. 7.3 EEPROM Registers
    4. 7.4 Register Descriptions
      1. 7.4.1  MODE_CTRL Register (CS Register Page: 0x0) (CS Offset: 0x0C) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      2. 7.4.2  PADC_DATA_LSB and PADC_DATA_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x20, 0x21) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      3. 7.4.3  TADC_DATA_LSB and TADC_DATA_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x24, 0x25) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      4. 7.4.4  DAC_REG_LSB and DAC_REG_MSB Registers (CS Register Page: 0x2) (CS Offset: 0x30, 0x31) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      5. 7.4.5  TC and NL Compensation Coefficient (hx, gx, nx, and mx) Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: see ) (EEPROM Offset: see )
      6. 7.4.6  Digital Filter Coefficient (ax and bx) Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: See ) (EEPROM Offset: See )
      7. 7.4.7  NORMAL_LOW_LSB and NORMAL_LOW_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x02, 0x03)
      8. 7.4.8  NORMAL_HIGH_LSB and NORMAL_HIGH_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x04, 0x05)
      9. 7.4.9  LOW_CLAMP_LSB and LOW_CLAMP_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x06, 0x07)
      10. 7.4.10 HIGH_CLAMP_LSB and HIGH_CLAMP_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x00, 0x01)
      11. 7.4.11 PADC_GAIN_LSB and PADC_GAIN_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x02, 0x03)
      12. 7.4.12 PADC_OFFSET_LSB and PADC_OFFSET_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x6) (EEPROM Offset: 0x04, 0x05)
      13. 7.4.13 DAC_FAULT_LSB and DAC_FAULT_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x02, 0x03)
      14. 7.4.14 TADC_GAIN_LSB and TADC_GAIN_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x04, 0x05)
      15. 7.4.15 TADC_OFFSET_LSB and TADC_OFFSET_MSB Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x9) (EEPROM Offset: 0x06, 0x07)
      16. 7.4.16 SERIAL_NUMBER_BYTE0/1/2/3 Registers (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0xA) (EEPROM Offset: 0x00, 0x01, 0x02, 0x03)
      17. 7.4.17 DAC_CONFIG Register (CS Register Page: 0x2) (CS Offset: 0x39) (EEPROM Page: 0x4) (EEPROM Offset: 0x00)
      18. 7.4.18 OP_STAGE_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x3B) (EEPROM Page: 0x4) (EEPROM Offset: 0x01)
      19. 7.4.19 TEST_CTRL Register (CS Register Page: 0x02) (CS Offset: 0x67) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      20. 7.4.20 BRDG_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x46) (EEPROM Page: 0x4) (EEPROM Offset: 0x02)
      21. 7.4.21 P_GAIN_SELECT Register (CS Register Page: 0x2) (CS Offset: 0x47) (EEPROM Page: 0x4) (EEPROM Offset: 0x03)
      22. 7.4.22 T_GAIN_SELECT Register (CS Register Page: 0x2) (CS Offset: 0x48) (EEPROM Page: 0x4) (EEPROM Offset: 0x04)
      23. 7.4.23 TEMP_CTRL Register (CS Register Page: 0x2) (CS Offset: 0x4C) (EEPROM Page: 0x4) (EEPROM Offset: 0x05)
      24. 7.4.24 TEMP_SE Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x5) (EEPROM Offset: 0x00)
      25. 7.4.25 DIAG_ENABLE Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x04)
      26. 7.4.26 AFEDIAG_MASK Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x07)
      27. 7.4.27 AFEDIAG_CFG Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x06)
      28. 7.4.28 AFEDIAG (CS Register Page: 0x2) (CS Offset: 0x5A) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      29. 7.4.29 EEPROM_LOCK Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0x8) (EEPROM Offset: 0x05)
      30. 7.4.30 EEPROM_PAGE_ADDRESS Register (CS Register Page: 0x5) (CS Offset: 0x88) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      31. 7.4.31 EEPROM_CTRL Register (CS Register Page: 0x5) (CS Offset: 0x89) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      32. 7.4.32 EEPROM_STATUS Register (CS Register Page: 0x5) (CS Offset: 0x8B) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      33. 7.4.33 EEPROM_CRC Register (CS Register Page: 0x5) (CS Offset: 0x8A) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      34. 7.4.34 EEPROM_CRC_STATUS Register (CS Register Page: 0x5) (CS Offset: 0x8C) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      35. 7.4.35 EEPROM_CRC_VALUE_CALC Register (CS Register Page: 0x5) (CS Offset: 0x8D) (EEPROM Page: N/A) (EEPROM Offset: N/A)
      36. 7.4.36 EEPROM_CRC_VALUE_USER Register (CS Register Page: N/A) (CS Offset: N/A) (EEPROM Page: 0xF) (EEPROM Offset: 0x07)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Harness Open-Wire Diagnostics
    2. 8.2 Typical Applications
      1. 8.2.1 4-mA to 20-mA Current Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components
          2. 8.2.1.2.2 Programming and EEPROM Settings
        3. 8.2.1.3 Application Curve
      2. 8.2.2 0-V to 10-V Absolute Voltage Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Components
          2. 8.2.2.2.2 Programming and EEPROM Settings
      3. 8.2.3 0-V to 5-V Ratiometric Voltage Output
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 External Components
          2. 8.2.3.2.2 Programming and EEPROM Settings
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
6.5.1.3.3.2 Read Operation

The read operation requires two consecutive OWI frames to move data from the target to the controller. The first frame is the read-initialization frame. This frame tells the target to retrieve data from a particular register location within the target device and prepare to send the data over the OWI. The command field of the read-initialization frame specifies which control and status register page to read from. The first data field specifies which address within that control and status register page to read from. Sending data fields two to eight is optional. The target ignores those additional data fields. The data are not sent until the controller commands the data to be sent in the subsequent frame called the read-response frame. During the read-response frame, the data direction changes from controller → target to target → controller immediately after the read-response command field is sent. Enough time elapses between the command field and data field to allow the signal drivers to change direction. This wait time is 20 µs, and the timer for this wait time is located on the target device. After this wait time is complete, the target transmits the requested data. The controller device is expected to have switched its signal drivers and to be ready to receive data. Figure 6-19 and Figure 6-20 show the two read frames that are required to complete a read operation.

PGA300 OWI Read-Initialization FrameFigure 6-19 OWI Read-Initialization Frame
PGA300 OWI Read-Response FrameFigure 6-20 OWI Read-Response Frame