SLFS047D February   1984  – March 2026 TLC556 , TLC556M

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: VDD = 2V for TLC556C, VDD = 3V for TLC556I
    6. 5.6  Electrical Characteristics: VDD = 5V
    7. 5.7  Electrical Characteristics: VDD = 15V
    8. 5.8  Switching Characteristics
    9. 5.9  Typical Characteristics: TLC556C and TLC556I
    10. 5.10 Typical Characteristics: TLC556M
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram (Each Timer)
    3. 6.3 Feature Description
      1. 6.3.1 Monostable Operation
      2. 6.3.2 Astable Operation
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Designing for Improved ESD Performance
    2. 7.2 Typical Applications
      1. 7.2.1 Pulse-Width Modulation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Pulse-Position Modulation
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Description

The TLC556 series are CMOS monolithic timing circuits. The timers are fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2MHz. Because of high input impedance, this device supports smaller timing capacitors than those supported by the NE556. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC556 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering.

Although the CMOS output is capable of sinking over 100mA and sourcing over 10mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This feature minimizes the need for the large decoupling capacitors required by the NE556.

The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from −40°C to +85°C. The TLC556M is characterized for operation over the full military temperature range of −55°C to +125°C.

Device Information
PART NUMBER RATING PACKAGE(1)
TLC556C Catalog D (SOIC, 14)
N (PDIP, 14)
TLC556I Industrial D (SOIC, 14)
N (PDIP, 14)
TLC556M Military D (SOIC, 14)
FK (LCCC, 20)
J (CDIP, 14)
N (PDIP, 14)
For more information, see Section 10.

 

TLC556 TLC556M Simplified Schematic Simplified Schematic