4 Which System Factors Can Influence the Result

Although a narrow input pulse width scenario can be destructive from a product lifetime point of view and must be avoided, it is hard to provide an exact value of minimum input pulse width even for a known operating condition. This is because of the numerous variables like PCB layout and decoupling capacitor placement can affect the internal voltage spike significantly. However, some simple math can provide a starting point for estimating the minimum pulse width that can be applied to the gate driver input in a given system.

For the narrow on pulse scenario, internal VDD pad voltage can be assumed from Equation 1.

Where:

• VDD_supply refers to bias power voltage which is used to supply the gate drive circuit, normally from flyback for the high voltage topology.
• L_bondwire refers to the IC internal bond wire parasitic inductance, usually around 5nH.
• L_PCB refers to the external PCB trace parasitic from supply to the pinout.

We can see several factors that can impact the internal overvoltage stress during narrow on pulse event, but the most important factor is the gate drive current at the switch OFF moment. Everything that increases the gate drive strength can also increase the $\frac{dI}{dt}$ which includes a larger gate voltage bias, small gate resistor (R_G), and larger gate capacitance. Most importantly, the gate current is not flat and linear during MOSFET turning on as shown in Figure 1-1, so the earlier MOSFET switches off, the larger the voltage spike that can be induced.

Narrow OFF pulse voltage spike estimation is a little bit more complicated. When the gate driver receives the turn ON command when the turn off period has not completed, the output voltage has not declined to zero. When the sinking current is interrupted, the spike seen on the Internal OUT pad is increased by the voltage drop across the PCB parasitic and bond wire inductance.

Where:

• VDD_internal refers to the internal VDD pad voltage.
• V_gatet is the gate driver output, it is also the gate voltage of the MOSFET. This voltage decrease as the off pulse extends and gate discharges.
• L_bondwire refers to the IC internal bond wire parasitic inductance, usually around 5nH.
• L_PCB refers to the external PCB trace parasitic from supply to the pinout.

When the off pulse is very short, $V_{gate}+(L_{bondwire}+L_{PCB})\frac{dI}{dt}$ is higher than internal VDD pad voltage.

As the off pulse extends, $V_{gate}+(L_{bondwire}+L_{PCB})\frac{dI}{dt}$ slowly decreases and the output follows the VDD internal voltage instead.