SLLA673 March   2025 MCF8315A , MCF8315C , MCF8315D , MCF8316A , MCF8316C-Q1 , MCF8316D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCF8315 Block Diagram and Pin Functions Introduction
  5. 2Fan Application Hardware Architecture
    1. 2.1 Total Discrete Hardware Design
    2. 2.2 MCU+Pre-Driver and External FET Design
    3. 2.3 All in One Design
  6. 3MCF8315 Hardware Design Guide for Fan Application
    1. 3.1 MCF8315 Power Part Design
    2. 3.2 MCF8315 Function Part Design
    3. 3.3 MCF8315 Communication and Output Part Design
    4. 3.4 MCF8315 Schematic Design Reference
    5. 3.5 MCF8315 Simplifies Peripheral Design
    6. 3.6 MCF8315 Thermal Performance Test
      1. 3.6.1 MCF8315 TSSOP Thermal Test With Inductance Version
  7. 4Summary
  8. 5References

3.2 MCF8315 Function Part Design

According to the pin definition requirements of the data sheet, the design requirements are as follows:

Table 3-3 MCF8315 Function Part Design
PinDescription
SPEEDThe SPEED pin can be configured to receive PWM, Frequency or VSP signals.
FGFG provides pulses proportional to the motor speed, and PULLUP_ENABLE sets the internal pull-up (3.3V)
nFAULT

The nFAULT (active low) pin provides the fault status of the device or motor in operation.

The MCF8315 provides a sound state machine protection and recovery mechanism, which can achieve device lock or self-recovery.

This design does not have an additional MCU system, and can be left floating or connected to an LED light for reminder

DRVOFF

When the pin is driven to high level, the MCF8315 stops driving the motor by setting MOSFET to a high impedance state,

when DRVOFF is driven high during motor operation, DRVOFF can be accompanied by faults such as no motor or abnormal back EMF

This design has no special requirements for stopping the motor, no external lead is required, and is directly connected to AGND (single point ground)

BRAKE

When BRAKE_INPUT defaults to 0h = hardware pin brake:

When the BRAKE pin is driven to high level, the MCF8315 enters the braking state.

When BRAKE_INPUT is set to 1h/2h:

1h = pin level is ignored according to BRAKE_PIN_MODE, and the braking state can be configured as low-side braking or alignment braking through BRAKE_PIN_MODE

2h = pin level is ignored, no braking/alignment

This design does not use this pin, the brake is set through the register, and is directly connected to AGND (single point ground)

DIR

The DIR pin determines the direction of motor rotation;

When the drive is high level, the sequence is OUT A → OUT B → OUT C

When the drive is low level, the sequence is OUT A → OUT C → OUT B

This design does not use the DIR pin, and is directly connected to AGND (single point ground) by configuring DIR_INPUT using the I2C interface

EXT_CLKFor low-cost applications, a speed loop accuracy of 3% is sufficient. This design does not use an external clock source, and is directly connected to AGND (single-point grounding)
EXT_WDThis design does not have an additional MCU system, and is directly connected to AGND (single-point grounding)
DACOUTThis design does not need to obtain an analog voltage equivalent to a digital variable, does not need to be led out, and can be left floating.