SLLSFS2 September   2025 TCAN6062-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings, IEC Transients
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Characteristics
    6. 5.6 Supply Characteristics
    7. 5.7 Dissipation Ratings
    8. 5.8 Electrical Characteristics
    9. 5.9 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Signal Improvement Capability
      2. 7.1.2 CAN XL and FAST Mode
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO (only for TCAN6062V-Q1)
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 STB (Standby)
      2. 7.3.2  CAN Bus States
      3. 7.3.3  Pulse-Width Modulation (PWM) for FAST Mode Signaling
        1. 7.3.3.1 PWM Detection and Timing
        2. 7.3.3.2 Transition from SIC Mode to FAST RX Mode
        3. 7.3.3.3 Transition from SIC Mode to FAST TX Mode
        4. 7.3.3.4 PWM Decoding
          1. 7.3.3.4.1 PWM Detection Resolution tDECODE
          2. 7.3.3.4.2 PWM Decoding in FAST RX Mode
          3. 7.3.3.4.3 PWM Decoding in FAST TX Mode
        5. 7.3.3.5 Transition from FAST RX/TX Modes to SIC Mode
      4. 7.3.4  Out-of-Bounds (OOB) Comparator
      5. 7.3.5  TXD Dominant Timeout (DTO)
      6. 7.3.6  CAN Bus short-circuit current limiting
      7. 7.3.7  Thermal Shutdown (TSD)
      8. 7.3.8  Undervoltage Lockout
      9. 7.3.9  Unpowered Device
      10. 7.3.10 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Standby Mode
        1. 7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
        1. 8.1.1.1 CAN Termination
      2. 8.1.2 Detailed Design Procedures
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
    2. 8.2 System Examples
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

7.3.2 CAN Bus States

The CAN bus has multiple logical states during operation. In SIC mode, the two states are recessive and dominant. See Figure 7-4. A dominant bus state occurs when the bus is driven differentially with VDIFF ≥ +1.5V and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input resistors (RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins. A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver.

The TCAN6062-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 7-4 and Figure 7-6.

In FAST mode, the CAN bus has two additional logical states: level_0 and level_1. See Figure 7-5. A level_0 bus state occurs when the bus is driven differentially with +1.5V ≥ VDIFF ≥ +0.6V, corresponding to a logic low on the RXD pin and a low duty cycle on TXD as shown in Figure 7-10. A level_1 bus state occurs when the bus is driven differentially with -0.6V ≥ VDIFF ≥ -1.5V, corresponding to a logic high on the RXD pin and a high duty cycle on RXD as shown in Figure 7-11.

TCAN6062-Q1 TCAN6062V-Q1 Bus States in SIC Mode and Standby ModeFigure 7-4 Bus States in SIC Mode and Standby Mode
TCAN6062-Q1 TCAN6062V-Q1 Bus States in FAST ModeFigure 7-5 Bus States in FAST Mode
TCAN6062-Q1 TCAN6062V-Q1 Simplified Recessive Common Mode Bias Unit and Receiver
A. Normal Mode
B. Standby Mode
Figure 7-6 Simplified Recessive Common Mode Bias Unit and Receiver