SLLSFS2 September   2025 TCAN6062-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings, IEC Transients
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Characteristics
    6. 5.6 Supply Characteristics
    7. 5.7 Dissipation Ratings
    8. 5.8 Electrical Characteristics
    9. 5.9 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Signal Improvement Capability
      2. 7.1.2 CAN XL and FAST Mode
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO (only for TCAN6062V-Q1)
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 STB (Standby)
      2. 7.3.2  CAN Bus States
      3. 7.3.3  Pulse-Width Modulation (PWM) for FAST Mode Signaling
        1. 7.3.3.1 PWM Detection and Timing
        2. 7.3.3.2 Transition from SIC Mode to FAST RX Mode
        3. 7.3.3.3 Transition from SIC Mode to FAST TX Mode
        4. 7.3.3.4 PWM Decoding
          1. 7.3.3.4.1 PWM Detection Resolution tDECODE
          2. 7.3.3.4.2 PWM Decoding in FAST RX Mode
          3. 7.3.3.4.3 PWM Decoding in FAST TX Mode
        5. 7.3.3.5 Transition from FAST RX/TX Modes to SIC Mode
      4. 7.3.4  Out-of-Bounds (OOB) Comparator
      5. 7.3.5  TXD Dominant Timeout (DTO)
      6. 7.3.6  CAN Bus short-circuit current limiting
      7. 7.3.7  Thermal Shutdown (TSD)
      8. 7.3.8  Undervoltage Lockout
      9. 7.3.9  Unpowered Device
      10. 7.3.10 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Standby Mode
        1. 7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
        1. 8.1.1.1 CAN Termination
      2. 8.1.2 Detailed Design Procedures
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
    2. 8.2 System Examples
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

5.8 Electrical Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ unless otherwise noted) 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver - SIC mode
VCANH(D) Dominant output voltage SIC mode 
 CANH VCC = 4.5 V to 5.5 V, TXD = 0 V, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CL = open		 2.75 3.5 4.5 V
VCANL(D) CANL 0.5 1.3 2.25 V
VCANH(D) Dominant output voltage SIC mode 
 CANH VCC = 4.75 V to 5.25 V, TXD = 0 V, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CL = open		 3 3.5 4.26 V
VCANL(D) CANL 0.75 1.3 2.01 V
VCANH(R), VCANL(R) Recessive output voltage SIC mode
 CANH, CANL w.r.t GND VCC = 4.5 V to 5.5 V, TXD = VIO, STB = 0 V
RL = open (no load), CL = open		 2 2.5 3 V
VCANH(R), VCANL(R) Recessive output voltage normal mode CANH, CANL w.r.t GND VCC = 4.75 V to 5.25 V, TXD = VIO, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω , CL = 4.7 nF		 2.256 2.5 2.756 V
VDIFF(D) Differential output voltage SIC mode
Dominant
 CANH - CANL TXD = 0 V, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CL = open		 1.5 3 V
TXD = 0 V, STB = 0 V
45 Ω ≤ RL ≤ 70 Ω, CL = open		 1.5 3.3 V
TXD = 0 V, STB = 0 V
RL = 2240 Ω, CL = open		 1.5 5 V
VDIFF(R) Differential output voltage SIC mode: Recessive
 CANH - CANL TXD = VIO, STB = 0 V
RL = open, CL = open		 –50 50 mV
TXD = VIO, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CSPLIT = 4.7 nF, CL = open		 –50 50 mV
VSYM Driver symmetry in SIC mode
(VO(CANH) + VO(CANL))/(VCANH(R) + VCANL(R))
 TXD toggling at 250 kHz, 1 MHz, 2.5 MHz, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CSPLIT = 4.7 nF, CL = open		 0.95 1.05 V/V
RID(DOM) Differential input resistance in SIC dominant phase TXD= 0 V, STB = 0 V  40 ohm
RSE_SIC_ACT_REC Single ended resistance CANH/CANL in active recessive phase 2 V ≤ VCANH/L ≤ VCC - 2 V
 37.5 50 66.5 Ω
RDIFF_SIC_ACT_REC Differential input resistance in active recessive phase 2 V ≤ VCANH/L ≤ VCC - 2 V
 75 100 133 Ω
VCANH(INACT) Bus output voltage standby mode
 CANH TXD = STB = VIO
RL = open, CL = open		 -0.1 0.1 V
VCANL(INACT) CANL -0.1 0.1 V
VDIFF(INACT) CANH - CANL -0.2 0.2 V
IOS Short-circuit bus output current,TXD is dominant or recessive or toggling, SIC mode
 V(CANH) = -15 V to 40 V, CANL = open, TXD = 0 V or VIO or 250 khz, 2.5 Mhz square wave –115 115 mA
V(CAN_L) = -15 V to 40 V, CANH = open, TXD = 0 V or VIO or 250 khz, 2.5 Mhz square wave –115 115 mA
Driver - FAST TX mode
VCAN_H0 Single ended voltage on CANH
 Level_0 TXD = Level_0 PWM symbol, STB = 0 V
45 Ω ≤ RL ≤ 60 Ω, CL = open		 2.55 3.51 V
VCAN_H1 Level_1 TXD = Level_1 PWM symbol, STB = 0 V
45 Ω ≤ RL ≤ 60 Ω, CL = open		 1.5 2.46 V
VCAN_L0 Single ended voltage on CANL
 Level_0 TXD = Level_0 PWM symbol, STB = 0 V
45 Ω ≤ RL ≤ 60 Ω, CL = open		 1.5 2.46 V
VCAN_L1 Level_1 TXD = Level_1 PWM symbol, STB = 0 V
45 Ω ≤ RL ≤ 60 Ω, CL = open		 2.55 3.51 V
VDIFF0 Differential output voltage Fast TX mode
 Level_0 TXD = Level_0 PWM symbol, STB = 0 V
45 Ω ≤ RL ≤ 60 Ω, CL = open		 0.6 1.5 V
VDIFF1 Level_1 TXD = Level_1 PWM symbol, STB = 0 V
45 Ω ≤ RL ≤ 60 Ω, CL = open		 -1.5 -0.6 V
VSYM Driver symmetry in Fast TX mode
(VO(CANH) + VO(CANL))/VCC
 TXD = PWM symbol of 5 Mbps, 10 Mbps, 20 Mbps, STB = 0 V
45 Ω ≤ RL ≤ 60 Ω, CSPLIT = 4.7 nF, CL = open		 0.95 1.05 V/V
IOS Short-circuit bus output current,TXD is Level_0 PWM or Level_1 PWM, Fast TX mode
 V(CANH) = -15 V to 40 V, CANL = open, TXD =Level_0 PWM or Level_1 PWM 5 Mbps, 10Mbps, 20Mbps –115 115 mA
V(CAN_L) = -15 V to 40 V, CANH = open, TXD =Level_0 PWM or Level_1 PWM 5 Mbps, 10Mbps, 20Mbps –115 115 mA
Receiver - SIC and Standby mode
VIT Input threshold voltage SIC mode
  -12 V ≤ VCM ≤ 12 V, STB= 0 V, RL = Open, CL = open
 		 500 900 mV
VIT(STB) Input threshold voltage standby mode
  -12 V ≤ VCM ≤ 12 V, STB= VIO, RL = Open, CL = open
 		 400 1150 mV
VDIFF_RX(D) SIC mode dominant state differential input voltage range
  -12 V ≤ VCM ≤ 12 V, STB= 0 V, RL = Open, CL = open
 		 0.9 9 V
VDIFF_RX(R) SIC mode recessive state differential input voltage range
 -12 V ≤ VCM ≤ 12 V, STB= 0 V, RL = Open, CL = open
 		 -4 0.5 V
VDIFF_RX(D_INACT) Standby mode dominant state differential input voltage range
 STB = VIO, -12 V ≤ VCM ≤ 12 V, RL = Open, CL = open
 		 1.15 9 V
VDIFF_RX(R_INACT) Standby mode recessive state differential input voltage range
 STB = VIO, -12 V ≤ VCM ≤ 12 V, RL = Open, CL = open
 		 -4 0.4 V
VHYS Hysteresis voltage for input threshold SIC mode
  -12 V ≤ VCM ≤ 12 V, STB= 0 V,
 		 100 mV
VCM Common mode range SIC, Fast and standby modes
 –12 12 V
ILKG(IOFF) Unpowered bus input leakage current CANH = CANL = 5 V,  VCC = VIO = GND  10 µA
CI Input capacitance to ground (CANH or CANL) TXD = VIO   50 pF
CID Differential input capacitance TXD = VIO   25 pF
RDIFF_PAS_REC Differential input resistance in passive recessive phase TXD = VIO, STB = 0 V -12 V ≤ VCM ≤ 12 V, Delta V/Delta I 12 100 kΩ
RSE_PAS_REC Single ended input resistance in passive recessive phase
(CANH or CANL)		 6 50 kΩ
RIN(M) Input resistance matching
2* [RIN(CANH) - RIN(CANL)] / [RIN(CANH) + RIN(CANL))] × 100 %		 V(CAN_H) = V(CAN_L) = 5 V –3 3 %
Receiver - FAST RX mode
VIT(FAST) Input threshold voltage Fast RX  -12 V ≤ VCM ≤ 12 V, STB= 0 V, RL = Open, CL = open
 		 -100 100 mV
VID(Level_0) Fast mode Level_0 state differential input voltage
range		  -12 V ≤ VCM ≤ 12 V, STB= 0 V, RL = Open, CL = open
 		 0.1 9 V
VID(Level_1) Fast mode Level_1 state differential input voltage
range		 -12 V ≤ VCM ≤ 12 V, STB= 0 V, RL = Open, CL = open
 		 -9 -0.1 V
OOB Comparator 
VIT(OOB) Input threshold voltage OOB comparator SIC mode
  -12 V ≤ VCM ≤ 12 V, STB= VIO
 		 -450 -250 mV
VID (OOB_Low) Low state differential input voltage range: OOB comparator SIC mode
  -12 V ≤ VCM ≤ 12 V, STB= VIO
 		 -8 -0.45 V
VID (OOB_High) High state differential input voltage range: OOB comparator SIC mode
  -12 V ≤ VCM ≤ 12 V, STB= VIO
 		 -0.25 8 V
TXD Terminal (CAN Transmit Data Input)
V(TXD)THRESH TXD input threshold voltage
 Devices with VIO 0.95*(VIO/2) 1.05*(VIO/2) V
V(TXD)LOW TXD input low voltage range Devices with VIO 0 0.95*(VIO/2) V
V(TXD)HIGH TXD input high voltage range Devices with VIO 1.05*(VIO/2) VIO V
R(TXD)PU Pull-up resistance on TXD input 20 80 kΩ
R(TXD)PD Pull-down resistance on TXD input 20 80 kΩ
mR(TXD) Pull-up and pull-down impedance matching 2 × (R(TXD)PU − R(TXD)PD) / (R(TXD)PU + R(TXD)PD)
 -0.05 0.05 Ohm/Ohm
IIH High-level input leakage current TXD = VIO = 5.5 V -1 1 µA
IIL Low-level input leakage current TXD = 0 V, VIO = 5.5 V -1 1 µA
ILKG(OFF) Unpowered leakage current TXD = 5.5 V, VCC = VIO = 0 V –1 1 µA
CI Input capacitance VIN = 0.4×sin(2×π×2×106×t) + 2.5 V 5 pF
RXD Terminal (CAN Receive Data Output)
VOH High-level output voltage IO = –1.5 mA, Devices with VIO 0.8 VIO   V
VOL Low-level output voltage Devices with VIO
IO = 1.5 mA, Devices with VIO		   0.2 VIO V
ILKG(OFF) Unpowered leakage current RXD = 5.5 V, VCC = VIO = 0 V –1 1 µA
STB Terminal (Standby Mode Input)
VIH High-level input voltage Devices with VIO 0.7 VIO V
VIL Low-level input voltage Devices with VIO 0.3 VIO V
IIH High-level input leakage current  VCC = VIO = STB = 5.5 V –2 2 µA
IIL Low-level input leakage current  VCC = VIO = 5.5 V, STB = 0 V –20 –2 µA
ILKG(OFF) Unpowered leakage current STB = 5.5V, VCC= VIO = 0 V –1 1 µA