SLLSFS2 September   2025 TCAN6062-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings, IEC Transients
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Characteristics
    6. 5.6 Supply Characteristics
    7. 5.7 Dissipation Ratings
    8. 5.8 Electrical Characteristics
    9. 5.9 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Signal Improvement Capability
      2. 7.1.2 CAN XL and FAST Mode
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO (only for TCAN6062V-Q1)
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 STB (Standby)
      2. 7.3.2  CAN Bus States
      3. 7.3.3  Pulse-Width Modulation (PWM) for FAST Mode Signaling
        1. 7.3.3.1 PWM Detection and Timing
        2. 7.3.3.2 Transition from SIC Mode to FAST RX Mode
        3. 7.3.3.3 Transition from SIC Mode to FAST TX Mode
        4. 7.3.3.4 PWM Decoding
          1. 7.3.3.4.1 PWM Detection Resolution tDECODE
          2. 7.3.3.4.2 PWM Decoding in FAST RX Mode
          3. 7.3.3.4.3 PWM Decoding in FAST TX Mode
        5. 7.3.3.5 Transition from FAST RX/TX Modes to SIC Mode
      4. 7.3.4  Out-of-Bounds (OOB) Comparator
      5. 7.3.5  TXD Dominant Timeout (DTO)
      6. 7.3.6  CAN Bus short-circuit current limiting
      7. 7.3.7  Thermal Shutdown (TSD)
      8. 7.3.8  Undervoltage Lockout
      9. 7.3.9  Unpowered Device
      10. 7.3.10 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Standby Mode
        1. 7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
        1. 8.1.1.1 CAN Termination
      2. 8.1.2 Detailed Design Procedures
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
    2. 8.2 System Examples
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

5.9 Switching Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ unless otherwise noted) 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
tFastTOSIC PWM detection time (Detection time to switch between FAST RX mode / FAST TX mode and SIC mode)
 Measured between 50% of TXD edge to next 50% edge (rising to rising or falling to falling) 210 245 ns
tSymbolNom PWM symbol acceptance length 45 205 ns
tSelect Mode pre-selection time 500 980 ns
tDecode PWM detection resolution  5 ns
tLogical_0_Tx PWM ratio detected as logical_0 FAST TX tDecode 0.5*tSymbolNom -  tDecode ns
tLogical_1_Tx PWM ratio detected as logical_1 FAST TX 0.5*tSymbolNom +  tDecode tSymbolNom -  tDecode ns
tLogical_Rx PWM ratio detected FAST RX tDecode tSymbolNom -  tDecode ns
t(LOOP1) SIC mode: Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CL(RXD) = 15 pF    95 155 ns
, normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω CL = 100 pF, CL(RXD) = 15 pF    100 165 ns
, normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CL(RXD) = 15 pF    105 175 ns
, normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CL(RXD) = 15 pF    120 190 ns
t(LOOP2) SIC mode: Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive  , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CL(RXD) = 15 pF    110 165 ns
, normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CL(RXD) = 15 pF    115 175 ns
, normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CL(RXD) = 15 pF    120 185 ns
, normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CL(RXD) = 15 pF    135 190 ns
tMODE Mode change time, from SIC to standby or from standby to SIC 30 µs
tProp(BusDom-BusLevel0) Propagation delay from mode change to bus level_0
(SIC mode to Fast TX mode)		 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 80 ns
tProp(BusLevel0-Rec) Propagation delay from mode change to bus recessive in FAST TX and FAST RX Mode
(Fast mode to SIC mode)		 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 325 ns
tΔBit(Bus)ADS/DAS Transmitter propagation delay symmetry ADS/DAS tΔBit(Bus)ADS/DAS = tProp(TXD-BusDom) – tProp(TXD-BusLevel0)
45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF
 -30 30 ns
tΔBit(RXD)ADS/DAS Receiver propagation delay symmetry ADS/DAS tΔBit(RXD)ADS/DAS = tProp(BusDom-RXD) – tProp(BusLevel0-RXD)
45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF
 -20 20 ns
tFILTER Filter time for a valid wake-up pattern 0.5 0.95 µs
tWAKE Bus wake-up timeout value 0.8 6 ms
tFlag Wake-up pattern signaling 250 µs
Driver Switching - SIC mode
tprop(TxD-busrec) Propagation delay time, low-to-high TXD edge to driver recessive (dominant to recessive)
 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 4.5 V to 5.5 V 45 75 ns
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 3 V to 3.6 V 45 75 ns
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 2.25 V to 2.75 V 45 75 ns
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 1.71 V to 1.89 V 45 80 ns
tprop(TxD-busdom) Propagation delay time, high-to-low TXD edge to driver dominant (recessive to dominant)
 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 4.5 V to 5.5 V 45 75 ns
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 3 V to 3.6 V 45 75 ns
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 2.25 V to 2.75 V 45 75 ns
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, VIO = 1.71 V to 1.89 V 45 80 ns
tsk(p) Pulse skew (|tprop(TxD-busrec) - tprop(TxD-busdom)|)
  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF 3.5 10 ns
tR Differential output signal rise time
 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF 22 30 ns
tF Differential output signal fall time
 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF 22 30 ns
tDOM Transmit dominant timeout (SIC mode) 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, STB = 0 V 0.8 6.0 ms
Receiver Switching - SIC mode
tprop(busrec-RXD) Propagation delay time, bus recessive input to RXD high output (dominant to recessive)

  STB = 0 V,
CL(RXD) = 15 pF, VIO = 4.5 V to 5.5 V		 67 90 ns
STB = 0 V, CL(RXD) = 15 pF, VIO = 3 V to 3.6 V 65 95 ns
STB = 0 V, CL(RXD) = 15 pF, VIO = 2.25 V to 2.75 V 70 105 ns
STB = 0 V, CL(RXD) = 15 pF, VIO = 1.71 V to 1.89 V 80 110 ns
tprop(busdom-RXD) Propagation delay time, bus dominant input to RXD low output (recessive to dominant)

 STB = 0 V,
CL(RXD) = 15 pF, VIO = 4.5 V to 5.5 V		 56 80 ns
STB = 0 V, CL(RXD) = 15 pF, VIO = 3 V to 3.6 V 61 90 ns
STB = 0 V, CL(RXD) = 15 pF, VIO = 2.25 V to 2.75 V 65 100 ns
STB = 0 V, CL(RXD) = 15 pF, VIO = 1.71 V to 1.89 V 75 110 ns
tR RXD output signal rise time STB = 0 V,
CL(RXD) = 15 pF		 7 20 ns
tF RXD output signal fall time 9 25 ns
tOOB_LOW (RXD) RXD low pulse width during fast data traffic, at the bit rate
10 Mbit/s		 tSymbolNom = 100 ns 30 ns
RXD low pulse width during fast data traffic, at the bit rate
20 Mbit/s		 tSymbolNom = 50 ns  15 ns
Driver Switching- FAST TX mode
tSIC_data Signal improvement time in FAST TX Mode 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 775 ns
tProp(TXD-BusLevel0) Propagation delay from TXD logical 0 to bus level_0
 VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 80 ns
VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 80 ns
VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 80 ns
VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 80 ns
tProp(TXD-BusLevel1) Propagation delay from TXD logical 1 to bus level_1
 VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 80 ns
VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 80 ns
VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 80 ns
VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 80 ns
tBusfall Fall time VDiff  45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  6 12 20 ns
tBusrise Rise time VDiff  45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  6 12 20 ns
tΔBit(Bus)Level1 Transmitted level_1 bit width variation in FAST TX Mode
 Bus level_1 bit length variation relative to TXD
tBit_data length
tΔBit(Bus)Level1 = tBit(Bus) Level1 – k * tBit_data
45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 		 - 5 5 ns
tΔBit(RxD)Logical1 Received logical 1 bit width variation in FAST TX Mode
 RXD logical 1 bit length variation relative to
TXD tBit_data length
tΔBit(RxD) Logical1 = tBit(RxD) Logical1 – k * tBit_data
45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 		 - 10 10 ns
Receiver Switching - FAST RX mode
tSIC_FAST_RX_dis SIC disable time after Fast RX detection VIO = 1.7 to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 80 ns
tProp(BusLevel0-RXD) Propagation delay from bus level_0 to RXD logical 0 VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 80 ns
VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 90 ns
VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 100 ns
VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 110 ns
tProp(BusLevel1-RXD) Propagation delay from bus level_1 to RXD logical 1 VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 80 ns
VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 
 TBD 90 ns
VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 100 ns
VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF  TBD 110 ns
tΔREC_Logical1 Logical 1 receiver timing symmetry in FAST RX Mode
 RXD logical 1 bit length variation relative to bus level_1 bit length
tΔREC_Logical1 = tBit(RxD) Logical1 - tBit( Bus) Level1
45 Ω ≤ RL ≤ 60 Ω, CL = 25 pF, CSPLIT = 0, CL(RXD) = 15 pF 		 -5 5 ns
Signal Improvement Timing Characteristics
tPAS_REC_START Start time of passive recessive
phase		 Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase  TBD 530 ns
tACT_REC_START Start time of active signal improvement phase Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase TBD 120 ns
tACT_REC_END End time of active signal improvement phase 355 TBD ns
tΔBit(Bus) Transmitted bit width variation
 tΔBit(Bus) = tBit(Bus) - tBit(TxD)
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)
 –10 10 ns
tΔBIT(RxD) Received bit width variation
 tΔBIT(RxD) = tBit(RxD) - tBit(TxD)
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)
 –30 20 ns
tΔREC Receiver timing symmetry
  tΔREC = tBit(RxD) - tBit(Bus)
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)
 –20 15 ns