SLLSG09 August   2026 TCAN2947-Q1 , TCAN2957-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 IEC ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Supply Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Requirements
    9. 6.9 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VCC1 Regulator
      2. 8.3.2  VCC2 Regulator
      3. 8.3.3  VEXCC Regulator
        1. 8.3.3.1 VEXCC in Stand-alone Configuration
        2. 8.3.3.2 VEXCC in Load-Sharing Conguration with VCC1
          1. 8.3.3.2.1 VEXCC: Unused Pins Configuration
      4. 8.3.4  CAN FD Transceiver
        1. 8.3.4.1 Driver and Receiver Function
        2. 8.3.4.2 CAN Bus Biasing
      5. 8.3.5  LIN Transceiver
        1. 8.3.5.1 LIN Transmitter Characteristics
        2. 8.3.5.2 LIN Receiver Characteristics
        3. 8.3.5.3 LIN Termination
      6. 8.3.6  High-Side Switches
      7. 8.3.7  WAKE and Voltage Monitoring Input
        1. 8.3.7.1 WAKE Pins Alternate Configurations
          1. 8.3.7.1.1 VBAT monitoring
          2. 8.3.7.1.2 Direct Drive
          3. 8.3.7.1.3 Using Wake Pins For Hardware ID Function
      8. 8.3.8  nRST Pin
      9. 8.3.9  LIMP Output
      10. 8.3.10 Interrupt Function
      11. 8.3.11 SW Pin
      12. 8.3.12 GFO Pin
      13. 8.3.13 Wake Features
        1. 8.3.13.1 CAN Bus Wake via CRXD Request (BWRR) in Sleep Mode
        2. 8.3.13.2 LIN Bus Wake
        3. 8.3.13.3 Local Wake Up (LWU) via WAKEx Input Terminal
          1. 8.3.13.3.1 Static Wake
          2. 8.3.13.3.2 Cyclic Sensing Wake
        4. 8.3.13.4 Cyclic Wake
        5. 8.3.13.5 Direct Drive in Sleep Mode
      14. 8.3.14 Long Duration Timer
      15. 8.3.15 Safety Features
        1. 8.3.15.1  Watchdog
          1. 8.3.15.1.1 Watchdog Error Counter and Action
          2. 8.3.15.1.2 Watchdog SPI Programming
            1. 8.3.15.1.2.1 Watchdog Configuration Registers Lock and Unlock
          3. 8.3.15.1.3 Watchdog Timing
          4. 8.3.15.1.4 Question and Answer Watchdog
            1. 8.3.15.1.4.1 WD Question and Answer Basic Information
            2. 8.3.15.1.4.2 Question and Answer Register and Settings
            3. 8.3.15.1.4.3 WD Question and Answer Value Generation
              1. 8.3.15.1.4.3.1 Answer Comparison
              2. 8.3.15.1.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
            4. 8.3.15.1.4.4 Question and Answer WD Example
              1. 8.3.15.1.4.4.1 Example Configuration for Desired Behavior
              2. 8.3.15.1.4.4.2 Example of Performing a Question and Answer Sequence
        2. 8.3.15.2  Under/Over Voltage Lockout and Unpowered Device
          1. 8.3.15.2.1 Under-voltage
            1. 8.3.15.2.1.1 VSUP and VHSS Under-voltage
            2. 8.3.15.2.1.2 VCC1 Under-voltage
            3. 8.3.15.2.1.3 VCC2 and VEXCC Under-voltage
            4. 8.3.15.2.1.4 VCAN Under-voltage
          2. 8.3.15.2.2 VCC1, VCC2 and VEXCC Over-voltage
          3. 8.3.15.2.3 VCC1, VCC2 and VEXCC Short Circuit
        3. 8.3.15.3  Analog Built-in Self Test (ABIST)
        4. 8.3.15.4  Clock Monitoring
        5. 8.3.15.5  Bandgap Cross-Monitoring
        6. 8.3.15.6  Device Reset
        7. 8.3.15.7  Floating Terminals
        8. 8.3.15.8  LIN Bus Stuck Dominant System Fault: False Wake Up Lockout
        9. 8.3.15.9  Thermal Shutdown
        10. 8.3.15.10 Bus Fault Detection and Communication
      16. 8.3.16 SPI Communication
        1. 8.3.16.1 Cyclic Redundancy Check
        2. 8.3.16.2 Chip Select Not (nCS):
        3. 8.3.16.3 SPI Clock Input (SCK):
        4. 8.3.16.4 SPI Data Input (SDI):
        5. 8.3.16.5 SPI Data Output (SDO):
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Restart Mode
      5. 8.4.5 Fail-safe Mode
      6. 8.4.6 Sleep Mode
  10. 9 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Normal Mode Application Note
        2. 10.2.1.2 Standby Mode Application Note
        3. 10.2.1.3 LTXD Dominant State Timeout Application Note
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Detailed Design Procedure
        2. 10.2.2.2 LIN Detailed Design Procedures
      3. 10.2.3 Device Brownout information
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 LIN Transceiver Physical Layer Standards
      3. 11.1.3 EMC Requirements:
      4. 11.1.4 Conformance Test Requirements:
      5. 11.1.5 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
    2. 13.2 Mechanical Data
8.3.15.2.1.4 VCAN Under-voltage

If VCAN drops below UVCAN under-voltage detection, the CAN transmitter switches off and disengage from the bus until VCAN has recovered. The CAN receiver is still active. See Figure 8-37 on how the device behaves. The device is designed to be an "ideal passive" or “no load” to the CAN bus if the device is unpowered. The bus terminals (CANH, CANL) have extremely low leakage currents when the device is unpowered, so they do not load the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains operational. Logic terminals also have low leakage currents when the device is unpowered, so the terminals do not load other circuits which may remain powered.

The UVLO circuit monitors both rising and falling edge of a power rail when ramping and declining.

TCAN2945-Q1 TCAN2947-Q1 TCAN2955-Q1 TCAN2957-Q1 UVCAN State DiagramFigure 8-37 UVCAN State Diagram
Note:
  • UVCAN comparator is only enabled when the CAN transceiver is programmed on or in listen.