SLLSG47 May   2026 TCAN4572-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specification
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings, IEC ESD and ISO Transient Specification
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Supply Characteristics
    7. 5.7 Electrical Characteristics
    8. 5.8 Timing Requirements
    9. 5.9 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDD Pin
      2. 7.3.2  VCC Pin
      3. 7.3.3  VIO Pin
      4. 7.3.4  GND
      5. 7.3.5  RST Pin
      6. 7.3.6  SPI CRC Feature
      7. 7.3.7  OSC1, OSC2 Pins and Automatic Clock Detection
      8. 7.3.8  Manual Clock Selection
      9. 7.3.9  nWKRQ, nINT1 Pin
      10. 7.3.10 nINT Interrupt Pin
      11. 7.3.11 CANH and CANL Bus Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Sleep Mode
        1. 7.4.3.1 Sleep Mode: Register Data and Access
        2. 7.4.3.2 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
      4. 7.4.4 Test Modes
      5. 7.4.5 Failsafe Feature
      6. 7.4.6 Protection Features
        1. 7.4.6.1 Driver and Receiver Function
        2. 7.4.6.2 Floating Terminals
        3. 7.4.6.3 CAN TXD_INT Dominant Timeout (DTO)
        4. 7.4.6.4 CAN Bus Short Circuit Current Limiting
        5. 7.4.6.5 Thermal Shutdown
        6. 7.4.6.6 Under Voltage Lockout (UVLO) and Unpowered Device
          1. 7.4.6.6.1 UVCC
          2. 7.4.6.6.2 UVIO
          3. 7.4.6.6.3 Fault and M_CAN Core Behavior:
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Chip Select Not (nCS):
        2. 7.5.1.2 SPI Clock Input (SCLK):
        3. 7.5.1.3 SPI Data Input (SDI):
        4. 7.5.1.4 SPI Data Output (SDO)
        5. 7.5.1.5 SPI Header Format and Byte Order
        6. 7.5.1.6 SPI Cyclic Redundancy Check (CRC)
      2. 7.5.2 MCAN CAN FD Controller and MRAM Programming
      3. 7.5.3 MRAM Allocation
      4. 7.5.4 MCAN DMA Improvements
  9. 8 Application and Implementation
    1. 8.1 Application Design Consideration
      1. 8.1.1 Crystal and Clock Input Requirements
      2. 8.1.2 Bus Loading, Length and Number of Nodes
      3. 8.1.3 CAN Termination
        1. 8.1.3.1 Termination
        2. 8.1.3.2 CAN Bus Biasing
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Requirements
      2. 8.2.2 Detailed Design Procedures
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 DEVICE_INFO_AND_SPI Registers
      1. 9.1.1 DEVICE_ID0 Register (Address = 0x0) [Reset = 0x4E414354]
      2. 9.1.2 DEVICE_ID1 Register (Address = 0x4) [Reset = 0x32373534]
      3. 9.1.3 DEVICE_REV Register (Address = 0x8) [Reset = 0x04000300]
      4. 9.1.4 SPI_IR_STATUS Register (Address = 0xC) [Reset = 0x00000000]
      5. 9.1.5 SPI_IE Register (Address = 0x10) [Reset = 0x00000000]
      6. 9.1.6 SPI_CRC_CONF Register (Address = 0x14) [Reset = 0x00000000]
      7. 9.1.7 SPI_CRC_SEED Register (Address = 0x18) [Reset = 0x00000000]
      8. 9.1.8 SCRATCHPAD Register (Address = 0x1C) [Reset = 0x00000000]
    2. 9.2 DEVICE_CONFIG Registers
      1. 9.2.1 DEV_MODE_PINS Register (Address = 0x800) [Reset = 0x00000040]
      2. 9.2.2 TIMESTAMP_PRESCALER Register (Address = 0x804) [Reset = 0x00000002]
      3. 9.2.3 SCRATCHPAD Register (Address = 0x808) [Reset = 0x00000000]
      4. 9.2.4 ECC_CONFIG Register (Address = 0x80C) [Reset = 0x00000000]
      5. 9.2.5 IP_EN_CNTRL Register (Address = 0x814) [Reset = 0x000000X0]
      6. 9.2.6 INT_DEVICE Register (Address = 0x820) [Reset = 0x00100000]
      7. 9.2.7 INT_MCAN Register (Address = 0x824) [Reset = 0x00000000]
      8. 9.2.8 INT_DEVICE_EN Register (Address = 0x830) [Reset = 0xFFFFFF01]
      9. 9.2.9 INT_DEVICE_EN Register (Address = 0x830) [Reset = 0xFFFFFF01]
    3. 9.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820 to 16'h0830
      1. 9.3.1 Interrupts (address = h0820) [reset = h00100000]
      2. 9.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
      3. 9.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
    4. 9.4 CAN_CONTROLLER Registers
      1. 9.4.1  CREL Register (Address = 0x1000) [Reset = 0x32380608]
      2. 9.4.2  ENDN Register (Address = 0x1004) [Reset = 0x87654321]
      3. 9.4.3  DBTP Register (Address = 0x100C) [Reset = 0x00000A33]
      4. 9.4.4  TEST Register (Address = 0x1010) [Reset = 0x00000000]
      5. 9.4.5  RWD Register (Address = 0x1014) [Reset = 0x00000000]
      6. 9.4.6  CCCR Register (Address = 0x1018) [Reset = 0x00000001]
      7. 9.4.7  NBTP Register (Address = 0x101C) [Reset = 0x06000A03]
      8. 9.4.8  TSCC Register (Address = 0x1020) [Reset = 0x00000000]
      9. 9.4.9  TSCV Register (Address = 0x1024) [Reset = 0x00000000]
      10. 9.4.10 TOCC Register (Address = 0x1028) [Reset = 0xFFFF0000]
      11. 9.4.11 TOCV Register (Address = 0x102C) [Reset = 0x0000FFFF]
      12. 9.4.12 ECR Register (Address = 0x1040) [Reset = 0x00000000]
      13. 9.4.13 PSR Register (Address = 0x1044) [Reset = 0x00000707]
      14. 9.4.14 TDCR Register (Address = 0x1048) [Reset = 0x00000000]
      15. 9.4.15 IR Register (Address = 0x1050) [Reset = 0x00000000]
      16. 9.4.16 IE Register (Address = 0x1054) [Reset = 0x00000000]
      17. 9.4.17 ILS Register (Address = 0x1058) [Reset = 0x00000000]
      18. 9.4.18 ILE Register (Address = 0x105C) [Reset = 0x00000000]
      19. 9.4.19 GFC Register (Address = 0x1080) [Reset = 0x00000000]
      20. 9.4.20 SIDFC Register (Address = 0x1084) [Reset = 0x00000000]
      21. 9.4.21 XIDFC Register (Address = 0x1088) [Reset = 0x00000000]
      22. 9.4.22 XIDAM Register (Address = 0x1090) [Reset = 0x3FFFFFFF]
      23. 9.4.23 HPMS Register (Address = 0x1094) [Reset = 0x00000000]
      24. 9.4.24 NDAT1 Register (Address = 0x1098) [Reset = 0x00000000]
      25. 9.4.25 NDAT2 Register (Address = 0x109C) [Reset = 0x00000000]
      26. 9.4.26 RXF0C Register (Address = 0x10A0) [Reset = 0x00000000]
      27. 9.4.27 RXF0S Register (Address = 0x10A4) [Reset = 0x00000000]
      28. 9.4.28 RXF0A Register (Address = 0x10A8) [Reset = 0x00000000]
      29. 9.4.29 RXBC Register (Address = 0x10AC) [Reset = 0x00000000]
      30. 9.4.30 RXF1C Register (Address = 0x10B0) [Reset = 0x00000000]
      31. 9.4.31 RXF1S Register (Address = 0x10B4) [Reset = 0x00000000]
      32. 9.4.32 RXF1A Register (Address = 0x10B8) [Reset = 0x00000000]
      33. 9.4.33 RXESC Register (Address = 0x10BC) [Reset = 0x00000000]
      34. 9.4.34 TXBC Register (Address = 0x10C0) [Reset = 0x00000000]
      35. 9.4.35 TXFQS Register (Address = 0x10C4) [Reset = 0x00000000]
      36. 9.4.36 TXESC Register (Address = 0x10C8) [Reset = 0x00000000]
      37. 9.4.37 TXBRP Register (Address = 0x10CC) [Reset = 0x00000000]
      38. 9.4.38 TXBAR Register (Address = 0x10D0) [Reset = 0x00000000]
      39. 9.4.39 TXBCR Register (Address = 0x10D4) [Reset = 0x00000000]
      40. 9.4.40 TXBTO Register (Address = 0x10D8) [Reset = 0x00000000]
      41. 9.4.41 TXBCF Register (Address = 0x10DC) [Reset = 0x00000000]
      42. 9.4.42 TXBTIE Register (Address = 0x10E0) [Reset = 0x00000000]
      43. 9.4.43 TXBCIE Register (Address = 0x10E4) [Reset = 0x00000000]
      44. 9.4.44 TXEFC Register (Address = 0x10F0) [Reset = 0x00000000]
      45. 9.4.45 TXEFS Register (Address = 0x10F4) [Reset = 0x00000000]
      46. 9.4.46 TXEFA Register (Address = 0x10F8) [Reset = 0x00000000]
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
        1. 10.1.1.1 CAN Transceiver Physical Layer Standards:
        2. 10.1.1.2 EMC requirements:
        3. 10.1.1.3 Conformance Test requirements:
        4. 10.1.1.4 Support Documents
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Tape and Reel Information
    3. 12.3 Mechanical Data

9.2.7 INT_MCAN Register (Address = 0x824) [Reset = 0x00000000]

INT_MCAN is shown in Figure 9-15 and described in Table 9-19.

Return to the Summary Table.

Figure 9-15 INT_MCAN Register
3130292827262524
RESERVEDARAPEDPEAWDIBOEW
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
2322212019181716
EPELOBEUBECDRXTOOMRAFTSW
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
15141312111098
TEFLTEFFTEFWTEFNTFETCFTCHPM
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
76543210
RF1LRF1FRF1WRF1NRF0LRF0FRF0WRF0N
R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0R-0x0
Table 9-19 INT_MCAN Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0x0 Reserved
29ARAR0x0 Access to reserved address
28PEDR0x0 Protocol error in data phase (data bit time is used)
27PEAR0x0 Protocol error in arbitration phase (nominal bit time is used)
26WDIR0x0 MRAM watchdog interrupt
25BOR0x0 Bus off interrupt
24EWR0x0 Warning status
23EPR0x0 Error passive
22ELOR0x0 Error logging overflow
21BEUR0x0 Bit error uncorrected
20BECR0x0 Bit error corrected
19DRXR0x0 Message stored to dedicated RX buffer
18TOOR0x0 Timeout occurred
17MRAFR0x0 Message RAM access failure
16TSWR0x0 Timestamp wraparound
15TEFLR0x0 TX event FIFO element lost
14TEFFR0x0 TX event FIFO full
13TEFWR0x0 TX event FIFO watermark reached
12TEFNR0x0 TX Event FIFO new entry
11TFER0x0 TX FIFO empty
10TCFR0x0 Transmission cancellation finished
9TCR0x0 Transmission Completed
8HPMR0x0 High priority message
7RF1LR0x0 RX FIFO 1 message lost
6RF1FR0x0 RX FIFO 1 full
5RF1WR0x0 RX FIFO 1 watermark reached
4RF1NR0x0 RX FIFO 1 new message
3RF0LR0x0 RX FIFO 0 message lost
2RF0FR0x0 RX FIFO 0 full
1RF0WR0x0 RX FIFO 0 watermark reached
0RF0NR0x0 RX FIFO 0 new message