JFET op amps consist of a JFET input stage and BJTs in the gain and output stages. These devices typically have the highest V_OS and temperature drift of the 3 process types. This can be attributed to the transconductance of the JFET, which is lower than that of the BJT (see Gray and Meyer [2]). DC precision is sacrificed in JFET op amps, so they are generally used when a high input impedance or AC performance is needed.

The JFET differential input circuit is the same as the bipolar circuit shown in Figure 4-1 with JFET transistors substituted for Q₁ and Q₂. The collector load resistor R_C now becomes the drain load resistor R_D. Again, Kirchoff's Voltage Law is used to derive Equation 13. V_GS is defined in Equation 14, assuming the JFET is a square-law device, and substituted into Equation 13 to get Equation 8.

The JFET is much more sensitive to changes in bias current from mismatches in the channels of Q₁, Q₂, R_D, and I_REF, resulting in a higher overall V_OS than the bipolar differential input stage. V_OS for the JFET process is primarily created by mismatching of the pinch-off voltages (V_P) of the devices as represented in the first term (in parentheses) of Equation 8. The channel doping level and thickness are the components of V_P that create this error. The second and third terms also have some error introduced by V_P as well as error introduced by I_D through the mismatching of R_D and I_DSS caused by the channel geometry and doping levels of the input transistors. The overall result is a difference in the V_GS voltages of Q₁ and Q₂, causing V_OS to appear across the op amp inputs.

Overall V_OS is calculated for JFET similar to bipolar using Equation 5.