Some devices offer internal calibration of the input offset voltage and drift. These features are called autocalibration, zero-drift, auto-zero, chopper, or Self-Cal™. Texas Instruments zero-drift op amps are implemented using auto-zero or chopper-stabilized techniques. They both have an internal control loop that nulls out the input offset voltage that is caused by change in temperature, supply voltage, input common-mode or output voltage. For this reason, zero-drift amplifiers not only achieve single-digit μV offset and tens of nV/°C drift but also extremely high AOL, CMRR, PSRR (above 140dB).

In case of auto-zero, a main amplifier, A1, and the nulling amplifier, A2, each have an associated input offset voltage that is stored during sample phase on C₁ and C₂, respectively – see Figure 6-4. In the auto-zero phase the charge from both caps is being transferred to null the total offset. The internal high-order filter is used to minimize switching noise. Some of the first Texas Instruments auto-zero op amps are OPA335 and OPA735 with their maximum offset of ±5uV and maximum drift of ±0.05μV/°C.

Figure 6-5 shows the input stage of a chopper op amp. The amplifier is a conventional transconductance stage with differential input and differential output current. Chopping is accomplished with commutating switches on the input and output that synchronously reverse the polarity. The offset voltage of the transconductance stage is inside the input switching network, thus its contribution to output is periodically reversed by the output switches. The output current caused by offset voltage causes the voltage on C₁ to ramp up and down at an equal rate. The internal logic assures equal up and down ramp times so the average output voltage on C₁ is zero. Since both differential input and output stages are reversed simultaneously, the net effect on the output capacitor, C₁, is in-phase signal and zero average offset voltage.

New-generation choppers are dramatically quieter, incorporating a switched-capacitor filter with multiple notches aligned with the chopping frequency and its odd harmonics, while the high frequency input signal bypasses chopping (DC) stage all together using fast-forward (GM_FF) stage – see Figure 6-6. A superior filtering is accomplished by integrating a charge for a full clock cycle before transferring its charge to the next stage of the op amp. Integrated over a full up-down cycle, its net value is zero. In the frequency domain, this creates a sinc(x) or sin(x)/x filter response with nulls that precisely align with the fundamental and all harmonics of the triangle wave. Since 1/f (flicker) noise is merely a slow time-varying offset voltage, choppers virtually eliminate this increased noise-spectral density in the low-frequency range. The chopping shifts the baseband signal to the chopping frequency beyond the input stage’s 1/f region. Thus, the low-frequency signal range of choppers has a noise-spectral density equal to that of the amplifier’s broadband frequency noise.

Some of the recent Texas Instruments’ high-voltage chopper amplifiers like OPA182 achieve maximum offset voltage of ±4μV and maximum drift of ±12nV/°C with typical AOL, CMRR and PSRR above 166dB. TI’s low-voltage supply choppers like OPA387 maximum offset and drift limits are ±2μV and ±12nV/°C, respectively, while its typical CMRR, PSRR and AOL are all above 145dB. However, the input bias current is affected by the charge and discharge current glitches of the input zero-drift circuitry. This effectively creates repetitive IB current pulses of opposite polarity in 100's of pA. For this reason, the zero-drift amplifiers are not recommended for applications with high source impedances. The amount of IB current sunk or sourced from the input stage is dependent on the combination of input impedance (resistance and capacitance), as well as the balance and matching of these impedances across the two inputs. These positive and negative input current pulses, integrated by the input capacitance, may cause a shift in the apparent "average bias current" that leads to offset voltage shift. Since the input bias average current may be dependent on the input impedance, it is difficult to estimate what the actual input bias current is without knowing the end-circuit and associated parasitic capacitors. For this reason, in order to minimize the offset voltage shift caused by unequal positive and negative I_B pulses, it is important to match the input impedances between the two input terminals.