Most op amps have some form of offset trim that is performed during the manufacturing process. The op amps with bipolar and JFET inputs use a Zener diode trim technique to reduce the offset voltages. This method places a network of Zener diodes with series resistance in parallel with the biasing collector-drain resistor. The Zener diodes are then blown as required to increase the parallel resistance, lowering the overall biasing resistance in the desired leg of the circuit.

Op amps with CMOS inputs use a fuse-link trim network because a CMOS diode structure is not available. This method places a fuse in series with resistors, rather than a Zener diode. When the fuse is removed, the parallel resistance is decreased, and the biasing resistance is increased in the desired leg of the circuit.

Laser trim is another alternative that is often used to lower V_OS. A resistor network is created, and then portions of it are eliminated to increase or decrease the resistance and balance the currents in each leg of the differential pair. This is a more exact technique and is reserved for precision parts.

Devices in multiple op amp packages (duals and quads) often have less trim capability. This is because the space is reduced on the silicon die for adding trim networks. Multiple op amps on a package, particularly the quads, use up all available space. One or more op amps on a quad package can therefore have a higher offset rating than the single or dual packaged devices, although good design and layout of the IC often prevents this.