The TLC272 and TLC277 are specified with a minimum and a maximum input voltage that, if exceeded at either input, can cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit is specified at V_DD – 1V at T_A = 25°C and at V_DD – 1.5V at all other temperatures.

The use of the polysilicon-gate process and the careful input circuit design gives the TLC272 and TLC277 very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1μV/month,including the first month of operation.

Because of the extremely high input impedance and resulting low bias current requirements, the TLC272 and TLC277 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias current requirements and cause a degradation in device performance. Including guard rings around inputs (similar to those of Figure 5-4 in the Section 5 section) is good practice. These guards must be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 6-4).

Connect unused amplifiers as grounded unity-gain followers to avoid possible oscillation.