SLOSE97B November   2024  – February 2025 DRV81008-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
      1. 5.5.1 SPI Timing Requirements
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Pins
        1. 6.3.1.1 Input Pins
        2. 6.3.1.2 nSLEEP Pin
      2. 6.3.2 Power Supply
        1. 6.3.2.1 Modes of Operation
          1. 6.3.2.1.1 Power-up
          2. 6.3.2.1.2 Sleep mode
          3. 6.3.2.1.3 Idle mode
          4. 6.3.2.1.4 Active mode
          5. 6.3.2.1.5 Limp Home mode
        2. 6.3.2.2 Reset condition
      3. 6.3.3 Power Stage
        1. 6.3.3.1 Switching Resistive Loads
        2. 6.3.3.2 Inductive Output Clamp
        3. 6.3.3.3 Maximum Load Inductance
        4. 6.3.3.4 Switching Channels in parallel
      4. 6.3.4 Protection and Diagnostics
        1. 6.3.4.1 Undervoltage on VM
        2. 6.3.4.2 Overcurrent Protection
        3. 6.3.4.3 Over Temperature Protection
        4. 6.3.4.4 Over Temperature Warning
        5. 6.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 6.3.4.6 Reverse Polarity Protection
        7. 6.3.4.7 Over Voltage Protection
        8. 6.3.4.8 Output Status Monitor
      5. 6.3.5 SPI Communication
        1. 6.3.5.1 SPI Signal Description
          1. 6.3.5.1.1 Chip Select (nSCS)
            1. 6.3.5.1.1.1 Logic high to logic low Transition
            2. 6.3.5.1.1.2 Logic low to logic high Transition
          2. 6.3.5.1.2 Serial Clock (SCLK)
          3. 6.3.5.1.3 Serial Input (SDI)
          4. 6.3.5.1.4 Serial Output (SDO)
        2. 6.3.5.2 Daisy Chain Capability
        3. 6.3.5.3 SPI Protocol
        4. 6.3.5.4 SPI Registers
          1. 6.3.5.4.1  Standard Diagnosis Register
          2. 6.3.5.4.2  Output control register
          3. 6.3.5.4.3  Input 0 Mapping Register
          4. 6.3.5.4.4  Input 1 Mapping Register
          5. 6.3.5.4.5  Input Status Monitor Register
          6. 6.3.5.4.6  Open Load Current Control Register
          7. 6.3.5.4.7  Output Status Monitor Register
          8. 6.3.5.4.8  Configuration Register
          9. 6.3.5.4.9  Output Clear Latch Register
          10. 6.3.5.4.10 Configuration Register 2
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Typical Application
      2. 7.1.2 Suggested External Components
      3. 7.1.3 Application Plots
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Package Footprint Compatibility
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

DRV81008-Q1 24-Pin HTSSOP (PWP) Top View Figure 4-1 24-Pin HTSSOP (PWP) Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME

NO.
VM

20

P

Analog supply voltage for power stage and protection circuits

VDD

24

P

Digital supply voltage for SPI

GND

5, 8, 17

G

Ground pin

nSCS

1

I

Serial chip select. An active low on this pin enables the serial interface communications. Integrated pull-up to VDD.

SCLK

2

I

Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Integrated pull-down to GND.

SDI

3

I

Serial data input. Data is captured on the falling edge of SCLK. Integrated pull-down to GND.

SDO

4

O

Serial data output. Data is shifted out on the rising edge of SCLK.

nSLEEP

21

I

Logic high activates Idle mode. Integrated pull-down to GND.

IN0

23

I

Connected to channel 2 by default and in Limp Home mode. Integrated pull-down to GND.

IN1

22

I

 Connected to channel 3 by default and in Limp Home mode. Integrated pull-down to GND.

OUT0

6

O

 Drain of low-side FET (channel 0)

OUT2

7

O

 Drain of low-side FET (channel 2)

OUT4

9

O

 Drain of low-side FET (channel 4)

OUT6

12

O

 Drain of low-side FET (channel 6)

OUT7

13

O

 Drain of low-side FET (channel 7)

OUT5

16

O

 Drain of low-side FET (channel 5)

OUT3

18

O

 Drain of low-side FET (channel 3)

OUT1

19

O

 Drain of low-side FET (channel 1)

NC

10, 11, 14, 15

-

No connect, internally not bonded

PAD

-

-

Exposed pad. Connect the exposed pad to PCB ground for cooling and EMC.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power