SLUS900F December 2008 – August 2026 BQ32000
PRODUCTION DATA
Description – Clock seconds and STOP bit
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | BIT(S) |
| STOP | 10_SECOND | 1_SECOND | Name | |||||
| r/w | r/w | r/w | Read/Write | |||||
| 0 | X | X | X | X | X | X | X | Initial |
| UC | UC | UC | UC | UC | UC | UC | UC | Cycle |
| STOP | Oscillator stop. The STOP bit is used to force the oscillator to stop oscillating. STOP is set to 0 on initial application of power, on all subsequent power cycles STOP remains unchanged. On initial power application STOP can be written to 1 and then written to 0 to force start the oscillator. | |
| 0 | Normal | |
| 1 | Stop | |
| 10_SECOND | BCD of tens of seconds. The 10_SECOND bits are the BCD representation of the number of tens of seconds on the clock. Valid values are 0 to 5. If invalid data is written to 10_SECOND, the clock updates with invalid data in 10_SECOND until the counter rolls over; thereafter, the data in 10_SECOND is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. | |
| 1_SECOND | BCD of seconds. The 1_SECOND bits are the BCD representation of the number of seconds on the clock. Valid values are 0 to 9. If invalid data is written to 1_SECOND, the clock updates with invalid data in 1_SECOND until the counter rolls over; thereafter, the data in 1_SECOND is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. | |