SLUSA71B July   2010  – September 2025 UCC28070-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Bias Voltages (VCC and VREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft-Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio NCT and Current-Sense Resistor RS)
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = TA = –40°C to 125°C, VCC = 12V, GND = 0V, RRT = 75kΩ, RDMX = 68.1kΩ, RRDM = RSYN = 100kΩ, CCDR = 2.2nF,
CSS = CVREF = 0.1μF, CVCC = 1μF, IVREF = 0mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS SUPPLY
VCC(SHUNT) VCC shunt voltage(1) IVCC = 10mA 23 25 27 V
IVCC Supply current Disabled VVSENSE = 0V 7 mA
Enabled VVSENSE = 3V (switching) 9 12
UVLO VCC = 7V 200 µA
VCC = 9V 4 6 mA
VUVLO UVLO turnon threshold Measured at VCC (rising) 9.8 10.2 10.6 V
UVLO hysteresis Measured at VCC (falling) 1
VREF enable threshold Measured at VCC (rising) 7.5 8 8.5 V
LINEAR REGULATOR
VVREF Reference voltage No load IVREF = 0mA 5.82 6 6.18 V
Load rejection Measured as the change in VVREF
(IVREF = 0mA and –2mA)		 –12 12 mV
Line rejection Measured as the change in VVREF
(VCC = 11V and 20V, IVREF = 0μA)		 TA = 25°C –12 12
TA = –40°C to 125°C -16 16
PFC ENABLE
VEN Enable threshold Measured at VSENSE (rising) 0.65 0.75 0.85 V
Enable hysteresis 0.15
EXTERNAL PFC DISABLE
Disable threshold Measured at SS (falling) 0.5 0.6 V
Hysteresis VVSENSE > 0.85V 0.15 V
OSCILLATOR
Output phase shift Measured between GDA and GDB 179 180 181 °
VDMAX, VRT, VRDM Timing regulation voltages Measured at DMAX, RT, and RDM 2.91 3 3.09 V
fPWM PWM switching frequency RRT = 75kΩ, RDMX = 68.1kΩ,
VRDM = 0V, VCDR = 6V		 94 100 105 kHz
RRT = 24.9kΩ, RDMX = 22.6kΩ,
VRDM = 0V, VCDR = 6V		 270 290 330
DMAX Duty-cycle clamp RRT = 75kΩ, RDMX = 68.1kΩ,
VRDM = 0V, VCDR = 6V		 92% 95% 98%
Minimum programmable OFF-time RRT = 24.9kΩ, RDMX = 22.6kΩ,
VRDM = 0V, VCDR = 6V		 50 150 250 ns
fDM Frequency dithering magnitude change in fPWM RRDM = 316kΩ, RRT = 75kΩ 1 3 4.3 kHz
RRDM = 31.6kΩ, RRT = 24.9kΩ 23 30 36
fDR Frequency dithering rate of change in fPWM RRDM = 100kΩ, CCDR = 2.2nF 3 kHz
RRDM = 100kΩ, CCDR = 0.3nF 20
ICDR Dither rate current Measured at CDR (sink and source) ±10 μA
Dither disable threshold Measured at CDR (rising) 5 5.25 V
CLOCK SYNCHRONIZATION
VCDR SYNC enable threshold Measured at CDR (rising) 5 5.25 V
SYNC propagation delay VCDR = 6V, measured from RDM (rising) to GDx (rising) 50 100 ns
SYNC threshold (rising) VCDR = 6V, measured at RDM 1.2 1.5 V
SYNC threshold (falling) VCDR = 6V, measured at RDM 0.4 0.7 V
tSYNC SYNC pulse width, minimum Positive pulse 0.2 μs
Maximum SYNC pulse duty cycle(2) 50%
VOLTAGE AMPLIFIER
VSENSE voltage In regulation, TA = 25°C 2.94 3 3.06 V
VSENSE voltage In regulation 2.84 3 3.10 V
VSENSE input bias current In regulation 250 500 nA
VAO high voltage VVSENSE = 2.9V 4.8 5 5.2 V
VAO low voltage VVSENSE = 3.1V 0.05 0.5 V
gMV VAO transconductance VVSENSE = 2.8V to 3.2V, VVAO = 3V 70 μS
VAO sink current, overdriven limit VVSENSE = 3.5V, VVAO = 3V 30 μA
VAO source current, overdriven VVSENSE = 2.5V, VVAO = 3V, SS = 3V –30 μA
VAO source current,
overdriven limit + ISRC		 VVSENSE = 2.5V, VVAO = 3V –130 μA
Slew-rate correction threshold Measured as
VVSENSE (falling) / VVSENSE (regulation)		 92% 93% 95%
Slew-rate correction hysteresis Measured at VSENSE (rising) 3 9 mV
ISRC Slew-rate correction current Measured at VAO, in addition to
VAO source current		 –100 μA
Slew-rate correction enable threshold Measured at SS (rising) 4 V
VAO discharge current VVSENSE = 0.5V, VVAO = 1V 10 μA
SOFT START
ISS SS source current VVSENSE = 0.9V, VSS = 1V –10 μA
Adaptive source current VVSENSE = 2V, VSS = 1V –1.5 –2.5 mA
Adaptive SS disable Measured as VVSENSE – VSS –30 0 30 mV
SS sink current VVSENSE = 0.5V, VSS = 0.2V 0.5 0.9 mA
OVERVOLTAGE
VOVP OVP threshold Measured as
VVSENSE (rising) / VVSENSE (regulation)		 104% 106% 108%
OVP hysteresis Measured at VSENSE (falling) 100 mV
OVP propagation delay Measured between VSENSE (rising) and
GDx (falling)		 0.2 0.3 μs
ZERO-POWER
VZPWR Zero-power detect threshold Measured at VAO (falling) 0.65 0.75 V
Zero-power hysteresis 0.15 V
MULTIPLIER
kMULT Gain constant VVAO ≥ 1.5V, TA = 25°C 15.4 17 20 μA
VVAO = 1.2V, TA = 25°C 13.5 17 20.5
VVAO ≥ 1.5V 14 17 22
VVAO = 1.2V 12 17 22.5
IIMO Output current: zero VVINAC = 0.9VPK, VVAO = 0.8V –0.2 0 0.2 μA
VVINAC = 0V, VVAO = 5V –0.2 0 0.2
QUANTIZED VOLTAGE FEEDFORWARD
VLVL1 Level 1 threshold(3) Measured at VINAC (rising) 0.6 0.7 0.8 V
VLVL2 Level 2 threshold Measured at VINAC (rising) 1.0 V
VLVL3 Level 3 threshold Measured at VINAC (rising) 1.2 V
VLVL4 Level 4 threshold Measured at VINAC (rising) 1.4 V
VLVL5 Level 5 threshold Measured at VINAC (rising) 1.65 V
VLVL6 Level 6 threshold Measured at VINAC (rising) 1.95 V
VLVL7 Level 7 threshold Measured at VINAC (rising) 2.25 V
VLVL8 Level 8 threshold Measured at VINAC (rising) 2.6 V
CURRENT AMPLIFIERS
CAOx high voltage 5.75 6 V
CAOx low voltage 0.1 V
gMC CAOx transconductance 100 μS
CAOx sink current, overdriven 50 μA
CAOx source current, overdriven –50 μA
Input common mode range 0 3.6 V
Input offset voltage VRSYNTH = 6V, TA = 25°C –16 –8 0 mV
VRSYNTH = 6V -50 –8 40
Input offset voltage -50 –8 40 mV
Phase mismatch Measured as phase A input offset
minus phase B input offset		 TA = 25°C –12 0 12 mV
TA = –40°C to 125°C -20 14
CAOx pulldown current VVSENSE = 0.5V, VCAOx = 0.2V 0.5 0.9 mA
CURRENT SYNTHESIZER
VRSYNTH Regulation voltage VVSENSE = 3V, VVINAC = 0V 2.91 3 3.09 V
VVSENSE = 3V, VVINAC = 2.85V 0.1 0.15 0.2
Synthesizer disable threshold Measured at RSYNTH (rising) 5 5.25 V
VINAC input bias current 0.25 0.5 μA
PEAK CURRENT LIMIT
Peak current limit threshold VPKLMT = 3.3V, measured at CSx (rising) 3.27 3.3 3.33 V
Peak current limit propagation delay Measured between CSx (rising) and
GDx (falling) edges		 60 100 ns
PWM RAMP
VRMP PWM ramp amplitude 3.8 4 4.2 V
PWM ramp offset voltage TA = 25°C, RRT = 75kΩ 0.55 0.7 V
PWM ramp offset temperature coefficient –2 mV/°C
GATE DRIVE
GDA, GDB output voltage, high, clamped VCC = 20V, CLOAD = 1nF 11.5 13 15 V
GDA, GDB output voltage, high CLOAD = 1nF 10 10.5 V
GDA, GDB output voltage, low CLOAD = 1nF 0.2 0.3 V
Rise time GDx 1V to 9V, CLOAD = 1nF 18 30 ns
Fall time GDx 9V to 1V, CLOAD = 1nF 12 25 ns
GDA, GDB output voltage, UVLO VCC = 0V, IGDA, IGDB = 2.5mA 0.7 2 V
THERMAL SHUTDOWN
Thermal shutdown threshold 160 °C
Thermal shutdown recovery 140 °C
(1) Excessive VCC input voltage or current damages the device. The VCC clamp does not protect the device from an unregulated bias supply. If an unregulated supply is used, TI recommends a series-connected fixed positive-voltage regulator such as a UA78L15A. See Section 5.1 for the limits on VCC voltage and current.
(2) Due to the influence of the synchronization pulse-width on the programmability of the maximum PWM switching duty-cycle (DMAX), TI recommends to minimize the duty-cycle of the synchronization signal.
(3) The Level 1 threshold represents the zero-crossing detection threshold above which VINAC must rise to initiate a new input half-cycle, and below which VINAC must fall to terminate that half-cycle.